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/kernel/linux/linux-6.6/drivers/watchdog/
Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
31 #include <linux/clk.h>
35 #define DRV_NAME "sh-wdt"
39 * values, consult the asm-sh/watchdog.h. Overload this at module load
43 * something quite higher than 100 (or we need a proper high-res timer
46 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
47 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
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/kernel/linux/linux-5.10/drivers/watchdog/
Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
31 #include <linux/clk.h>
35 #define DRV_NAME "sh-wdt"
39 * values, consult the asm-sh/watchdog.h. Overload this at module load
43 * something quite higher than 100 (or we need a proper high-res timer
46 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
47 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
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Datlas7_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for CSR Atlas7
5 * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company.
8 #include <linux/clk.h>
39 struct clk *clk; member
47 counter = readl(wdt->base + ATLAS7_WDT_CNT); in atlas7_wdt_gettimeleft()
48 match = readl(wdt->base + ATLAS7_WDT_CNT_MATCH); in atlas7_wdt_gettimeleft()
49 delta = match - counter; in atlas7_wdt_gettimeleft()
51 return delta / wdt->tick_rate; in atlas7_wdt_gettimeleft()
59 counter = readl(wdt->base + ATLAS7_WDT_CNT); in atlas7_wdt_ping()
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/kernel/linux/linux-5.10/drivers/clk/
Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
13 #include <linux/clk-provider.h>
31 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument
33 return readl_relaxed(csr); in xgene_clk_read()
36 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument
38 writel_relaxed(data, csr); in xgene_clk_write()
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
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/kernel/linux/linux-6.6/drivers/clk/
Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
13 #include <linux/clk-provider.h>
31 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument
33 return readl_relaxed(csr); in xgene_clk_read()
36 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument
38 writel_relaxed(data, csr); in xgene_clk_write()
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 Registers(CSR) module represents a set of miscellaneous registers of a
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
19 should consider all subnodes of the CSR module as separate child devices.
23 pattern: "^syscon@[0-9a-f]+$"
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/kernel/linux/linux-6.6/drivers/spi/
Dspi-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
226 readl_relaxed((port)->regs + SPI_##reg)
228 writel_relaxed((value), (port)->regs + SPI_##reg)
230 writew_relaxed((value), (port)->regs + SPI_##reg)
261 struct clk *clk; member
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225 readl_relaxed((port)->regs + SPI_##reg)
227 writel_relaxed((value), (port)->regs + SPI_##reg)
229 writew_relaxed((value), (port)->regs + SPI_##reg)
259 struct clk *clk; member
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/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-sirf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
13 #include <linux/mmc/slot-gpio.h>
14 #include "sdhci-pltfm.h"
28 * CSR atlas7 and prima2 SD host version is not 3.0 in sdhci_sirf_set_bus_width()
29 * 8bit-width enable bit of CSR SD hosts is 3, in sdhci_sirf_set_bus_width()
42 u32 val = readl(host->ioaddr + reg); in sdhci_sirf_readl_le()
45 (host->mmc->caps & MMC_CAP_UHS_SDR50))) { in sdhci_sirf_readl_le()
64 ret = readw(host->ioaddr + reg); in sdhci_sirf_readw_le()
67 ret = readw(host->ioaddr + SDHCI_HOST_VERSION); in sdhci_sirf_readw_le()
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/kernel/linux/linux-6.6/drivers/net/wireless/ralink/rt2x00/
Drt2x00soc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2004 - 2009 Felix Fietkau <nbd@openwrt.org>
25 kfree(rt2x00dev->rf); in rt2x00soc_free_reg()
26 rt2x00dev->rf = NULL; in rt2x00soc_free_reg()
28 kfree(rt2x00dev->eeprom); in rt2x00soc_free_reg()
29 rt2x00dev->eeprom = NULL; in rt2x00soc_free_reg()
31 iounmap(rt2x00dev->csr.base); in rt2x00soc_free_reg()
36 struct platform_device *pdev = to_platform_device(rt2x00dev->dev); in rt2x00soc_alloc_reg()
41 return -ENODEV; in rt2x00soc_alloc_reg()
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/kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/
Drt2x00soc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2004 - 2009 Felix Fietkau <nbd@openwrt.org>
25 kfree(rt2x00dev->rf); in rt2x00soc_free_reg()
26 rt2x00dev->rf = NULL; in rt2x00soc_free_reg()
28 kfree(rt2x00dev->eeprom); in rt2x00soc_free_reg()
29 rt2x00dev->eeprom = NULL; in rt2x00soc_free_reg()
31 iounmap(rt2x00dev->csr.base); in rt2x00soc_free_reg()
36 struct platform_device *pdev = to_platform_device(rt2x00dev->dev); in rt2x00soc_alloc_reg()
41 return -ENODEV; in rt2x00soc_alloc_reg()
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/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-sirf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for CSR SiRFprimaII
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
14 #include <linux/clk.h>
70 struct clk *clk; member
92 for (i = 0; i < siic->read_cmd_len; i++) { in i2c_sirfsoc_read_data()
94 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); in i2c_sirfsoc_read_data()
95 siic->buf[siic->finished_len++] = in i2c_sirfsoc_read_data()
106 if (siic->msg_read) { in i2c_sirfsoc_queue_cmd()
107 while (((siic->finished_len + i) < siic->msg_len) in i2c_sirfsoc_queue_cmd()
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/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-prima2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * System timer for CSR SiRFprimaII
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
14 #include <linux/clk.h>
68 ce->event_handler(ce); in sirfsoc_timer_interrupt()
73 /* read 64-bit timer counter */
78 /* latch the 64-bit timer counter */ in sirfsoc_timer_read()
102 return next - now > delta ? -ETIME : 0; in sirfsoc_timer_set_next_event()
139 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) in sirfsoc_clocksource_resume()
143 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
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Dtimer-atlas7.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * System timer for CSR SiRFprimaII
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
15 #include <linux/clk.h>
81 ce->event_handler(ce); in sirfsoc_timer_interrupt()
86 /* read 64-bit timer counter */
138 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) in sirfsoc_clocksource_resume()
141 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
143 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], in sirfsoc_clocksource_resume()
178 ce->irq = irq; in sirfsoc_local_timer_starting_cpu()
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/kernel/linux/linux-5.10/drivers/iio/adc/
Dstm32-adc-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
12 #include <linux/clk.h>
25 #include "stm32-adc-core.h"
41 * struct stm32_adc_common_regs - stm32 common registers
42 * @csr: common status register offset
44 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
45 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
50 u32 csr; member
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/kernel/linux/linux-6.6/drivers/iio/adc/
Dstm32-adc-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
13 #include <linux/clk.h>
29 #include "stm32-adc-core.h"
45 * struct stm32_adc_common_regs - stm32 common registers
46 * @csr: common status register offset
48 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
49 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
54 u32 csr; member
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/kernel/linux/linux-5.10/drivers/dma/
Dxgene-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Applied Micro X-Gene SoC DMA engine Driver
13 #include <linux/clk.h>
15 #include <linux/dma-mapping.h>
26 /* X-Gene DMA ring csr registers and bit definations */
43 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
45 ((m) &= (~BIT(31 - (v))))
76 /* X-Gene DMA device csr registers and bit definitions */
105 /* X-Gene SoC EFUSE csr register and bit defination */
109 /* X-Gene DMA Descriptor format */
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/kernel/linux/linux-6.6/drivers/dma/
Dxgene-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Applied Micro X-Gene SoC DMA engine Driver
13 #include <linux/clk.h>
15 #include <linux/dma-mapping.h>
27 /* X-Gene DMA ring csr registers and bit definations */
44 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
46 ((m) &= (~BIT(31 - (v))))
77 /* X-Gene DMA device csr registers and bit definitions */
106 /* X-Gene SoC EFUSE csr register and bit defination */
110 /* X-Gene DMA Descriptor format */
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Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
6 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
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/kernel/linux/linux-5.10/drivers/clk/sirf/
Dclk-atlas6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock tree for CSR SiRFatlasVI
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
13 #include <linux/clk-provider.h>
18 #include "clk-common.c"
114 static struct clk *atlas6_clks[maxclk];
121 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); in atlas6_clk_init()
150 CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);
Dclk-prima2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock tree for CSR SiRFprimaII
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
13 #include <linux/clk-provider.h>
18 #include "clk-common.c"
113 static struct clk *prima2_clks[maxclk];
120 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); in prima2_clk_init()
149 CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-pllv4.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk-provider.h>
17 #include "clk.h"
52 u32 csr; in clk_pllv4_wait_lock() local
54 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, in clk_pllv4_wait_lock()
55 csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US); in clk_pllv4_wait_lock()
62 if (readl_relaxed(pll->base) & PLL_EN) in clk_pllv4_is_prepared()
75 mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); in clk_pllv4_recalc_rate()
79 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); in clk_pllv4_recalc_rate()
80 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); in clk_pllv4_recalc_rate()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
24 by Control and Status Registers(CSR) module in the SoC. The CSR
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
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/kernel/linux/linux-5.10/drivers/net/ethernet/qualcomm/emac/
Demac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
19 #include "emac-mac.h"
20 #include "emac-phy.h"
21 #include "emac-sgmii.h"
85 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
91 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
101 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx()
102 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx()
110 irq->mask |= rx_q->intr; in emac_napi_rtx()
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/kernel/linux/linux-6.6/drivers/net/ethernet/qualcomm/emac/
Demac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
18 #include "emac-mac.h"
19 #include "emac-phy.h"
20 #include "emac-sgmii.h"
84 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
90 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
100 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx()
101 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx()
109 irq->mask |= rx_q->intr; in emac_napi_rtx()
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