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/kernel/linux/linux-5.10/drivers/clk/nxp/
Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
165 static struct clk *clk[LPC32XX_CLK_MAX]; variable
167 .clks = clk,
171 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
253 * divider register does not contain information about selected rate.
329 enum clk_pll_mode mode; member
378 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) in lpc32xx_usb_clk_read() argument
[all …]
/kernel/linux/linux-6.6/drivers/clk/nxp/
Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
165 static struct clk *clk[LPC32XX_CLK_MAX]; variable
167 .clks = clk,
171 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
253 * divider register does not contain information about selected rate.
329 enum clk_pll_mode mode; member
378 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) in lpc32xx_usb_clk_read() argument
[all …]
/kernel/linux/linux-6.6/drivers/clk/davinci/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/davinci.h>
24 #include <linux/platform_data/clk-davinci-pll.h>
80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
81 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
[all …]
/kernel/linux/linux-5.10/drivers/clk/davinci/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/davinci.h>
24 #include <linux/platform_data/clk-davinci-pll.h>
80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
81 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-cdce925.c5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
7 * deliver using the standard clk framework. In addition, the device can
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
87 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; member
96 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate()
106 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
117 /* Can always deliver parent_rate in bypass mode */ in cdce925_pll_find_rate()
122 /* In PLL mode, need to apply min/max range */ in cdce925_pll_find_rate()
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/kernel/linux/linux-6.6/drivers/clk/
Dclk-cdce925.c5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
7 * deliver using the standard clk framework. In addition, the device can
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
87 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; member
96 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate()
106 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
117 /* Can always deliver parent_rate in bypass mode */ in cdce925_pll_find_rate()
122 /* In PLL mode, need to apply min/max range */ in cdce925_pll_find_rate()
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/kernel/linux/linux-6.6/drivers/clk/zynqmp/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Xilinx
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
47 * Return: Mode of PLL
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Marvell Ltd.
20 #include <linux/clk.h>
46 /* Register for the "Direct Mode" */
74 * have both is for managing the armada-370-spi case with old
96 struct clk *clk; member
97 struct clk *axi_clk;
105 return orion_spi->base + reg; in spi_reg()
139 orion_spi = spi_master_get_devdata(spi->master); in orion_spi_baudrate_set()
140 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
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/kernel/linux/linux-5.10/drivers/clk/zynqmp/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Xilinx
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
46 * Return: Mode of PLL
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Marvell Ltd.
19 #include <linux/clk.h>
45 /* Register for the "Direct Mode" */
73 * have both is for managing the armada-370-spi case with old
95 struct clk *clk; member
96 struct clk *axi_clk;
110 return orion_spi->base + reg; in spi_reg()
144 orion_spi = spi_controller_get_devdata(spi->controller); in orion_spi_baudrate_set()
145 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
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/kernel/linux/linux-5.10/drivers/clk/st/
Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
21 bool mode; member
29 /* Pre-divisor's gate */
31 /* Pre-divisor */
37 /* Asynchronous mode control */
[all …]
/kernel/linux/linux-5.10/drivers/clk/ti/
Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
[all …]
Dclkt_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
19 #include <linux/clk/ti.h>
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
30 #define DPLL_MULT_UNDERFLOW -1
51 #define DPLL_FINT_UNDERFLOW -1
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/kernel/linux/linux-6.6/drivers/gpu/ipu-v3/
Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
21 struct clk *clk_di; /* display input clock */
22 struct clk *clk_ipu; /* IPU bus clock */
23 struct clk *clk_di_pixel; /* resulting pixel clock */
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
[all …]
/kernel/linux/linux-5.10/drivers/gpu/ipu-v3/
Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
21 struct clk *clk_di; /* display input clock */
22 struct clk *clk_ipu; /* IPU bus clock */
23 struct clk *clk_di_pixel; /* resulting pixel clock */
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/frequency/
Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
35 adi,channel-spacing:
40 adi,power-up-frequency:
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/kernel/linux/linux-6.6/drivers/clk/ti/
Dclkt_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
19 #include <linux/clk/ti.h>
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
30 #define DPLL_MULT_UNDERFLOW -1
51 #define DPLL_FINT_UNDERFLOW -1
[all …]
Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
[all …]
/kernel/linux/linux-6.6/drivers/clk/renesas/
Drcar-gen3-cpg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
23 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
26 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
29 CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */
82 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
84 struct clk **clks, void __iomem *base,
87 unsigned int clk_extalr, u32 mode);
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
26 #include <linux/dma-mapping.h>
28 #include <linux/dma/mxs-dma.h>
30 #define DRIVER_NAME "mxs-i2c"
70 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
72 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
[all …]
/kernel/linux/linux-6.6/drivers/i2c/busses/
Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument
79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument
79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp()
[all …]
/kernel/linux/linux-5.10/drivers/clk/renesas/
Drcar-gen3-cpg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
22 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
69 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
71 struct clk **clks, void __iomem *base,
74 unsigned int clk_extalr, u32 mode);

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