| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | s3c64xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
58 old_freq = clk_get_rate(policy->clk) / 1000; in s3c64xx_cpufreq_set_target()
59 new_freq = s3c64xx_freq_table[index].frequency; in s3c64xx_cpufreq_set_target()
65 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
66 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
75 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
85 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
86 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
90 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
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| D | s3c24xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
7 * S3C24XX CPU Frequency scaling
18 #include <linux/clk.h>
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
39 static struct clk *_clk_mpll;
40 static struct clk *_clk_xtal;
41 static struct clk *clk_fclk;
42 static struct clk *clk_hclk;
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| D | vexpress-spc-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2019 ARM Ltd.
14 #include <linux/clk.h>
51 static struct clk *clk[MAX_CLUSTERS]; variable
56 static unsigned int clk_little_max; /* Maximum clock frequency (Little) */
93 u32 rate = clk_get_rate(clk[cur_cluster]) / 1000; in clk_get_cpu_rate()
130 ret = clk_set_rate(clk[new_cluster], new_rate * 1000); in ve_spc_cpufreq_set_rate()
136 * current design of the clk core layer. To work around this in ve_spc_cpufreq_set_rate()
138 * correct. This needs to be removed once clk core is fixed. in ve_spc_cpufreq_set_rate()
140 if (clk_get_rate(clk[new_cluster]) != new_rate * 1000) in ve_spc_cpufreq_set_rate()
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| D | s3c2416-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/clk.h>
25 struct clk *armdiv;
26 struct clk *armclk;
27 struct clk *hclk;
47 /* pseudo-frequency for dvs mode */
50 /* frequency to sleep and reboot in
61 /* S3C2416 only supports changing the voltage in the dvs-mode.
94 /* return our pseudo-frequency when in dvs mode */ in s3c2416_cpufreq_get_speed()
95 if (s3c_freq->is_dvs) in s3c2416_cpufreq_get_speed()
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| D | armada-37xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * CPU frequency scaling support for Armada 37xx platform.
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
26 #include "cpufreq-dt.h"
28 /* Clk register set */
124 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); in armada_37xx_cpu_freq_info_get()
166 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
186 * Find out the armada 37x supported AVS value whose voltage value is
187 * the round-up closest to the target voltage value.
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| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | s3c64xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
56 unsigned int new_freq = s3c64xx_freq_table[index].frequency; in s3c64xx_cpufreq_set_target()
63 old_freq = clk_get_rate(policy->clk) / 1000; in s3c64xx_cpufreq_set_target()
68 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
69 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
78 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
88 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
89 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
93 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
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| D | vexpress-spc-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2019 ARM Ltd.
14 #include <linux/clk.h>
48 static struct clk *clk[MAX_CLUSTERS]; variable
53 static unsigned int clk_little_max; /* Maximum clock frequency (Little) */
90 u32 rate = clk_get_rate(clk[cur_cluster]) / 1000; in clk_get_cpu_rate()
127 ret = clk_set_rate(clk[new_cluster], new_rate * 1000); in ve_spc_cpufreq_set_rate()
133 * current design of the clk core layer. To work around this in ve_spc_cpufreq_set_rate()
135 * correct. This needs to be removed once clk core is fixed. in ve_spc_cpufreq_set_rate()
137 if (clk_get_rate(clk[new_cluster]) != new_rate * 1000) in ve_spc_cpufreq_set_rate()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | qca,ar803x.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | qca,ar803x.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
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| D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | smp_twd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
101 * Updates clockevent frequency when the cpu frequency changes.
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| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | smp_twd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
101 * Updates clockevent frequency when the cpu frequency changes.
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gm20b.c | 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gm20b.c | 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
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| /kernel/linux/linux-5.10/drivers/sh/clk/ |
| D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
[all …]
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| /kernel/linux/linux-6.6/drivers/sh/clk/ |
| D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
57 struct clk *clk; member
65 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
67 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
74 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
76 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
85 * Fv is derived from the variable frequency output. The variable frequency
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| /kernel/linux/linux-6.6/drivers/pwm/ |
| D | pwm-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
56 struct clk *clk; member
64 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
66 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
73 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
75 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
84 * Fv is derived from the variable frequency output. The variable frequency
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr_smu_msg.c | 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 CTX->logger
65 } while (max_retries--); in dcn30_smu_wait_for_response()
199 /* Returns the actual frequency that was set in MHz, 0 on failure */
200 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t… in dcn30_smu_set_hard_min_by_freq() argument
204 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ in dcn30_smu_set_hard_min_by_freq()
205 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_min_by_freq()
207 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_min_by_freq()
212 smu_print("SMU Frequency set = %d MHz\n", response); in dcn30_smu_set_hard_min_by_freq()
217 /* Returns the actual frequency that was set in MHz, 0 on failure */
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| /kernel/linux/linux-6.6/drivers/net/mdio/ |
| D | mdio-mscc-miim.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/clk.h>
14 #include <linux/mdio/mdio-mscc-miim.h>
58 struct clk *clk; member
62 /* When high resolution timers aren't built-in: we can't use usleep_range() as
75 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_status()
78 ret = regmap_read(miim->regs, in mscc_miim_status()
79 MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val); in mscc_miim_status()
108 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_read()
114 goto out; in mscc_miim_read()
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-s3c2410.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
22 #include <linux/clk.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
111 struct clk *clk; member
127 .name = "s3c2410-i2c",
130 .name = "s3c2440-i2c",
133 .name = "s3c2440-hdmiphy-i2c",
143 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
144 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
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| D | i2c-digicolor.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
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| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| D | i2c-digicolor.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr_smu_msg.c | 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 CTX->logger
68 } while (max_retries--); in dcn30_smu_wait_for_response()
209 /* Returns the actual frequency that was set in MHz, 0 on failure */
210 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_… in dcn30_smu_set_hard_min_by_freq() argument
214 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ in dcn30_smu_set_hard_min_by_freq()
215 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_min_by_freq()
217 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_min_by_freq()
222 smu_print("SMU Frequency set = %d MHz\n", response); in dcn30_smu_set_hard_min_by_freq()
227 /* Returns the actual frequency that was set in MHz, 0 on failure */
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | mps2-timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
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