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/kernel/linux/linux-6.6/include/linux/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
[all …]
/kernel/linux/linux-5.10/include/linux/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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/kernel/linux/linux-6.6/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
19 'struct clk'.
29 clk, useful across many platforms, as well as an
30 implementation of the clock API in include/linux/clk.h.
31 Architectures utilizing the common struct clk should select
43 source "drivers/clk/versatile/Kconfig"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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/kernel/linux/linux-5.10/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
20 Select this option when the clock API in <linux/clk.h> is implemented
23 'struct clk'.
34 clk, useful across many platforms, as well as an
35 implementation of the clock API in include/linux/clk.h.
36 Architectures utilizing the common struct clk should select
48 source "drivers/clk/versatile/Kconfig"
76 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
86 multi-function device has one fixed-rate oscillator, clocked
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/kernel/linux/linux-6.6/drivers/clk/ux500/
Dclk-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
28 u8 source; member
36 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_prepare() local
38 return prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
[all …]
Du8500_of_clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
16 #include "reset-prcc.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
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/kernel/linux/linux-6.6/drivers/cpufreq/
Dspear-cpufreq.c2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
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/kernel/linux/linux-5.10/drivers/cpufreq/
Dspear-cpufreq.c2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
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/kernel/linux/linux-6.6/drivers/clk/tegra/
Dclk-super.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-super.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-nps.c7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
36 #include <linux/clk.h>
51 struct clk **clk) in nps_get_timer_clk() argument
55 *clk = of_clk_get(node, 0); in nps_get_timer_clk()
56 ret = PTR_ERR_OR_ZERO(*clk); in nps_get_timer_clk()
58 pr_err("timer missing clk\n"); in nps_get_timer_clk()
62 ret = clk_prepare_enable(*clk); in nps_get_timer_clk()
[all …]
Dtimer-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
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/kernel/linux/linux-5.10/drivers/net/can/mscan/
Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
19 #include <linux/clk.h>
36 { .compatible = "fsl,mpc5200-cdm", },
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
74 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
80 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
84 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
[all …]
/kernel/linux/linux-6.6/drivers/net/can/mscan/
Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
21 #include <linux/clk.h>
38 { .compatible = "fsl,mpc5200-cdm", },
55 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
66 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
76 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
82 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
86 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8qm-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
20 can1_lpcg: clock-controller@5ace0000 {
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/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
37 uint32_t source : 8; /* source index + 1 (0 == none) */ member
46 /* For fixed-factor ones */
66 .source = 1 + R9A06G032_##_src, .name = _n, \
70 .source = 1 + R9A06G032_##_src, .name = _n, \
77 .source = 1 + R9A06G032_##_src, .name = _n, \
81 .source = 1 + R9A06G032_##_src, .name = _n, \
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/kernel/linux/linux-6.6/drivers/clocksource/
Dtimer-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is disabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dfsl,sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
27 - items:
[all …]
/kernel/linux/linux-6.6/drivers/clk/renesas/
Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
26 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
33 * struct regbit - describe one bit in a register
35 * expressed in units of 32-bit words (not bytes),
43 * Since registers are aligned on 32-bit boundaries, the
44 * offset will be specified in 32-bit words rather than bytes.
48 * offset from bytes to 32-bit words.
[all …]
/kernel/linux/linux-6.6/sound/soc/fsl/
Dfsl_utils.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
42 return -EINVAL; in fsl_asoc_get_dma_channel()
44 if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) { in fsl_asoc_get_dma_channel()
46 return -EINVAL; in fsl_asoc_get_dma_channel()
55 * dai->platform name should already point to an allocated buffer. in fsl_asoc_get_dma_channel()
62 snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn", in fsl_asoc_get_dma_channel()
65 iprop = of_get_property(dma_channel_np, "cell-index", NULL); in fsl_asoc_get_dma_channel()
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