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Searched full:clk_main (Results 1 – 25 of 56) sorted by relevance

123

/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-mtk-disp.c47 struct clk *clk_main; member
77 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_config()
79 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_config()
86 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_config()
100 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_config()
105 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_config()
147 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_config()
157 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_enable()
159 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_enable()
166 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_enable()
[all …]
Dpwm-mediatek.c46 * @clk_main: the clock used by PWM core
55 struct clk *clk_main; member
80 ret = clk_prepare_enable(pc->clk_main); in pwm_mediatek_clk_enable()
91 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_enable()
104 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_disable()
238 pc->clk_main = devm_clk_get(&pdev->dev, "main"); in pwm_mediatek_probe()
239 if (IS_ERR(pc->clk_main)) { in pwm_mediatek_probe()
241 PTR_ERR(pc->clk_main)); in pwm_mediatek_probe()
242 return PTR_ERR(pc->clk_main); in pwm_mediatek_probe()
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-mtk-disp.c47 struct clk *clk_main; member
85 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
92 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_apply()
94 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", in mtk_disp_pwm_apply()
103 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
118 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_apply()
124 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
182 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_get_state()
184 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
191 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_get_state()
[all …]
Dpwm-mediatek.c48 * @clk_main: the clock used by PWM core
57 struct clk *clk_main; member
86 ret = clk_prepare_enable(pc->clk_main); in pwm_mediatek_clk_enable()
97 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_enable()
110 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_disable()
268 pc->clk_main = devm_clk_get(&pdev->dev, "main"); in pwm_mediatek_probe()
269 if (IS_ERR(pc->clk_main)) in pwm_mediatek_probe()
270 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main), in pwm_mediatek_probe()
/kernel/linux/linux-6.6/drivers/clk/renesas/
Dr9a09g011-cpg.c46 CLK_MAIN, enumerator
126 DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1),
127 DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2),
128 DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24),
155 DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
197 DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
199 DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4),
200 DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5),
201 DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6),
202 DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7),
[all …]
Dr8a779f0-cpg-mssr.c32 CLK_MAIN, enumerator
60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
64 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
65 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
Dr8a779g0-cpg-mssr.c32 CLK_MAIN, enumerator
69 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
70 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
71 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2_VAR, CLK_MAIN),
72 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
73 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
74 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
75 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
Dr7s9210-cpg-mssr.c50 CLK_MAIN, enumerator
62 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
63 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
174 case CLK_MAIN: in rza2_cpg_clk_register()
188 if (core->id == CLK_MAIN) in rza2_cpg_clk_register()
Dr8a77470-cpg-mssr.c27 CLK_MAIN, enumerator
43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
Dr8a7792-cpg-mssr.c30 CLK_MAIN, enumerator
45 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
46 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
47 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
48 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
Dr8a77970-cpg-mssr.c39 CLK_MAIN, enumerator
70 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
71 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
72 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
73 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
Dr8a7745-cpg-mssr.c27 CLK_MAIN, enumerator
43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
Dr8a77995-cpg-mssr.c31 CLK_MAIN, enumerator
58 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
62 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi260 clock-names = "clk_main", "clk_apb";
271 clock-names = "clk_main", "clk_apb";
282 clock-names = "clk_main", "clk_apb";
293 clock-names = "clk_main", "clk_apb";
304 clock-names = "clk_main", "clk_apb";
315 clock-names = "clk_main", "clk_apb";
326 clock-names = "clk_main", "clk_apb";
337 clock-names = "clk_main", "clk_apb";
352 clock-names = "clk_main", "clk_apb";
363 clock-names = "clk_main", "clk_apb";
[all …]
/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr7s9210-cpg-mssr.c50 CLK_MAIN, enumerator
62 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
63 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
174 case CLK_MAIN: in rza2_cpg_clk_register()
188 if (core->id == CLK_MAIN) in rza2_cpg_clk_register()
Dr8a774a1-cpg-mssr.c31 CLK_MAIN, enumerator
56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
57 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
Dr8a779a0-cpg-mssr.c57 CLK_MAIN, enumerator
82 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
99 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
100 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
101 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
Dr8a77980-cpg-mssr.c33 CLK_MAIN, enumerator
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
Dr8a77995-cpg-mssr.c31 CLK_MAIN, enumerator
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
Dr8a7792-cpg-mssr.c30 CLK_MAIN, enumerator
45 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
46 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
47 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
48 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
Dr8a77470-cpg-mssr.c27 CLK_MAIN, enumerator
43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
Dr8a7745-cpg-mssr.c27 CLK_MAIN, enumerator
43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
Dr8a77970-cpg-mssr.c39 CLK_MAIN, enumerator
70 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
71 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
72 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
73 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi325 clock-names = "clk_main", "clk_apb";
338 clock-names = "clk_main", "clk_apb";
351 clock-names = "clk_main", "clk_apb";
364 clock-names = "clk_main", "clk_apb";
377 clock-names = "clk_main", "clk_apb";
390 clock-names = "clk_main", "clk_apb";
403 clock-names = "clk_main", "clk_apb";
416 clock-names = "clk_main", "clk_apb";
461 clock-names = "clk_main", "clk_apb";
474 clock-names = "clk_main", "clk_apb";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/xilinx/
Dzynqmp_dma.txt10 - clock-names : List of input clocks "clk_main", "clk_apb"
23 clock-names = "clk_main", "clk_apb";

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