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/kernel/linux/linux-6.6/drivers/clk/ti/
Dclk-7xx.c44 …{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:…
129 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
215 "atl-clkctrl:0000:24",
226 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
302 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
[all …]
Dclk-44xx.c59 "abe-clkctrl:0018:26",
79 "abe-clkctrl:0020:26",
92 "abe-clkctrl:0028:26",
105 "abe-clkctrl:0030:26",
118 "abe-clkctrl:0038:26",
186 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
188 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
189 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
190 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
191 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
[all …]
Dclk-54xx.c53 "abe-clkctrl:0018:26",
73 "abe-clkctrl:0028:26",
86 "abe-clkctrl:0030:26",
99 "abe-clkctrl:0038:26",
139 { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
141 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
142 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
143 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
144 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
145 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
[all …]
Dclk-33xx.c19 "clk-24mhz-clkctrl:0000:0",
151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
207 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
241 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
243 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
[all …]
Dclk-43xx.c35 …{ AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl…
256 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
257 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
258 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
259 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
260 DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
261 DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
262 DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
263 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
264 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
[all …]
Dclkctrl.c3 * OMAP clkctrl clock support
250 /* Get clkctrl clock base name based on clkctrl_name or dts node */
258 /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */ in clkctrl_get_clock_name()
260 clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d", in clkctrl_get_clock_name()
280 /* l4per-clkctrl:1234:0 style naming based on node name */ in clkctrl_get_clock_name()
469 * compatible property for clkctrl.
494 if (!strncmp("ti,clkctrl-", compat, prefix_len)) { in clkctrl_get_name()
578 pr_err("%pOF not found from clkctrl data.\n", node); in _ti_omap4_clkctrl_setup()
601 * The code below can be removed when all clkctrl nodes use domain in _ti_omap4_clkctrl_setup()
719 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
[all …]
/kernel/linux/linux-5.10/drivers/clk/ti/
Dclk-7xx.c44 …{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:…
129 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
215 "atl-clkctrl:0000:24",
226 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
296 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
[all …]
Dclk-33xx.c27 "clk-24mhz-clkctrl:0000:0",
159 "l3-aon-clkctrl:0000:19",
160 "l3-aon-clkctrl:0000:30",
165 "l3-aon-clkctrl:0000:20",
175 "l3-aon-clkctrl:0000:22",
200 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
215 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
249 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
251 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
252 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
[all …]
Dclk-43xx.c43 …{ AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl…
263 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
264 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
265 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
266 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
267 DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
268 DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
269 DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
270 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
271 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
Dclkctrl.c2 * OMAP clkctrl clock support
258 /* Get clkctrl clock base name based on clkctrl_name or dts node */
266 /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */ in clkctrl_get_clock_name()
268 clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d", in clkctrl_get_clock_name()
288 /* l4per-clkctrl:1234:0 style naming based on node name */ in clkctrl_get_clock_name()
475 /* Get clock name based on compatible string for clkctrl */
484 if (!strncmp("ti,clkctrl-", compat, prefix_len)) { in clkctrl_get_name()
589 pr_err("%pOF not found from clkctrl data.\n", node); in _ti_omap4_clkctrl_setup()
612 * The code below can be removed when all clkctrl nodes use domain in _ti_omap4_clkctrl_setup()
730 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dti-clkctrl.txt1 Texas Instruments clkctrl clock binding
3 Texas Instruments SoCs can have a clkctrl clock controller for each
4 interconnect target module. The clkctrl clock controller manages functional
5 and interface clocks for each module. Each clkctrl controller can also
7 or more clock muxes. There is a clkctrl clock controller typically for each
10 The clock consumers can specify the index of the clkctrl clock using
11 the hardware offset from the clkctrl instance register space. The optional
12 clocks can be specified by clkctrl hardware offset and the index of the
19 - compatible : shall be "ti,clkctrl" or a clock domain specific name:
20 "ti,clkctrl-l4-cfg"
[all …]
Dartpec6.txt19 See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
20 - compatible: Should be "axis,artpec6-clkctrl"
35 clkctrl: clkctrl@f8000000 {
37 compatible = "axis,artpec6-clkctrl";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dti-clkctrl.txt1 Texas Instruments clkctrl clock binding
3 Texas Instruments SoCs can have a clkctrl clock controller for each
4 interconnect target module. The clkctrl clock controller manages functional
5 and interface clocks for each module. Each clkctrl controller can also
7 or more clock muxes. There is a clkctrl clock controller typically for each
10 The clock consumers can specify the index of the clkctrl clock using
11 the hardware offset from the clkctrl instance register space. The optional
12 clocks can be specified by clkctrl hardware offset and the index of the
19 - compatible : shall be "ti,clkctrl" or a clock domain specific name:
20 "ti,clkctrl-l4-cfg"
[all …]
Dartpec6.txt19 See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
20 - compatible: Should be "axis,artpec6-clkctrl"
35 clkctrl: clkctrl@f8000000 {
37 compatible = "axis,artpec6-clkctrl";
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap_hwmod_33xx_43xx_ipblock_data.c26 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) argument
254 CLKCTRL(am33xx_smartreflex0_hwmod, in omap_hwmod_am33xx_clkctrl()
256 CLKCTRL(am33xx_smartreflex1_hwmod, in omap_hwmod_am33xx_clkctrl()
258 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
259 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
260 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
261 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
262 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
263 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
264 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); in omap_hwmod_am33xx_clkctrl()
[all …]
/kernel/linux/linux-6.6/drivers/clk/mxs/
Dclk-imx28.c17 static void __iomem *clkctrl; variable
18 #define CLKCTRL clkctrl macro
20 #define PLL0CTRL0 (CLKCTRL + 0x0000)
21 #define PLL1CTRL0 (CLKCTRL + 0x0020)
22 #define PLL2CTRL0 (CLKCTRL + 0x0040)
23 #define CPU (CLKCTRL + 0x0050)
24 #define HBUS (CLKCTRL + 0x0060)
25 #define XBUS (CLKCTRL + 0x0070)
26 #define XTAL (CLKCTRL + 0x0080)
27 #define SSP0 (CLKCTRL + 0x0090)
[all …]
Dclk-imx23.c16 static void __iomem *clkctrl; variable
19 #define CLKCTRL clkctrl macro
22 #define PLLCTRL0 (CLKCTRL + 0x0000)
23 #define CPU (CLKCTRL + 0x0020)
24 #define HBUS (CLKCTRL + 0x0030)
25 #define XBUS (CLKCTRL + 0x0040)
26 #define XTAL (CLKCTRL + 0x0050)
27 #define PIX (CLKCTRL + 0x0060)
28 #define SSP (CLKCTRL + 0x0070)
29 #define GPMI (CLKCTRL + 0x0080)
[all …]
/kernel/linux/linux-5.10/drivers/clk/mxs/
Dclk-imx28.c17 static void __iomem *clkctrl; variable
18 #define CLKCTRL clkctrl macro
20 #define PLL0CTRL0 (CLKCTRL + 0x0000)
21 #define PLL1CTRL0 (CLKCTRL + 0x0020)
22 #define PLL2CTRL0 (CLKCTRL + 0x0040)
23 #define CPU (CLKCTRL + 0x0050)
24 #define HBUS (CLKCTRL + 0x0060)
25 #define XBUS (CLKCTRL + 0x0070)
26 #define XTAL (CLKCTRL + 0x0080)
27 #define SSP0 (CLKCTRL + 0x0090)
[all …]
Dclk-imx23.c16 static void __iomem *clkctrl; variable
19 #define CLKCTRL clkctrl macro
22 #define PLLCTRL0 (CLKCTRL + 0x0000)
23 #define CPU (CLKCTRL + 0x0020)
24 #define HBUS (CLKCTRL + 0x0030)
25 #define XBUS (CLKCTRL + 0x0040)
26 #define XTAL (CLKCTRL + 0x0050)
27 #define PIX (CLKCTRL + 0x0060)
28 #define SSP (CLKCTRL + 0x0070)
29 #define GPMI (CLKCTRL + 0x0080)
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dam33xx-clocks.dtsi546 l4ls_clkctrl: l4ls-clkctrl@38 {
547 compatible = "ti,clkctrl";
552 l3s_clkctrl: l3s-clkctrl@1c {
553 compatible = "ti,clkctrl";
558 l3_clkctrl: l3-clkctrl@24 {
559 compatible = "ti,clkctrl";
564 l4hs_clkctrl: l4hs-clkctrl@120 {
565 compatible = "ti,clkctrl";
570 pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
571 compatible = "ti,clkctrl";
[all …]
Dartpec6.dtsi45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
103 clkctrl: clkctrl@f8000000 { label
105 compatible = "axis,artpec6-clkctrl";
115 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
122 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
259 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
281 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
289 clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
290 <&clkctrl ARTPEC6_CLK_PTP_REF>;
335 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
[all …]
Ddra7xx-clocks.dtsi1523 mpu_clkctrl: mpu-clkctrl@20 {
1524 compatible = "ti,clkctrl";
1538 dsp1_clkctrl: dsp1-clkctrl@20 {
1539 compatible = "ti,clkctrl";
1553 ipu1_clkctrl: ipu1-clkctrl@20 {
1554 compatible = "ti,clkctrl";
1561 ipu_clkctrl: ipu-clkctrl@50 {
1562 compatible = "ti,clkctrl";
1576 dsp2_clkctrl: dsp2-clkctrl@20 {
1577 compatible = "ti,clkctrl";
[all …]
Dam43xx-clocks.dtsi771 l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
772 compatible = "ti,clkctrl";
777 l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
778 compatible = "ti,clkctrl";
783 l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
784 compatible = "ti,clkctrl";
798 mpu_clkctrl: mpu-clkctrl@20 {
799 compatible = "ti,clkctrl";
812 gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
813 compatible = "ti,clkctrl";
[all …]
Domap44xx-clocks.dtsi1034 compatible = "ti,clkctrl";
1048 compatible = "ti,clkctrl";
1062 compatible = "ti,clkctrl";
1079 compatible = "ti,clkctrl";
1093 compatible = "ti,clkctrl";
1107 compatible = "ti,clkctrl";
1121 compatible = "ti,clkctrl";
1135 compatible = "ti,clkctrl";
1149 compatible = "ti,clkctrl";
1163 compatible = "ti,clkctrl";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/axis/
Dartpec6.dtsi45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
103 clkctrl: clkctrl@f8000000 { label
105 compatible = "axis,artpec6-clkctrl";
115 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
122 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
259 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
281 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
289 clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
290 <&clkctrl ARTPEC6_CLK_PTP_REF>;
335 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
[all …]

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