Searched +full:clock +full:- +full:bindings (Results 1 – 25 of 1119) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-apq8084.h
19 - dt-bindings/reset/qcom,gcc-apq8084.h
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| D | maxim,max77686.txt | 1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
3 This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4 multi-function device. More information can be found in MFD DT binding
6 bindings/mfd/max77686.txt for MAX77686 and
7 bindings/mfd/max77802.txt for MAX77802 and
8 bindings/mfd/max77620.txt for MAX77620.
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
12 dt-bindings/clock/maxim,max77686.h.
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
17 dt-bindings/clock/maxim,max77802.h.
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| D | artpec6.txt | 1 * Clock bindings for Axis ARTPEC-6 chip
3 The bindings are based on the clock provider binding in
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 ----------------
9 There are two external inputs to the main clock controller which should be
10 provided using the common clock bindings.
11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference clock (optional).
14 Main clock controller
15 ---------------------
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| D | qcom,sc7180-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core Clock Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm LPASS core clock control module which supports the clocks and
17 - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
22 - qcom,sc7180-lpasshm
23 - qcom,sc7180-lpasscorecc
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| D | exynos4-clock.txt | 1 * Samsung Exynos4 Clock Controller
3 The Exynos4 clock controller generates and supplies clock to various controllers
4 within the Exynos4 SoC. The clock binding described here is applicable to all
9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume.
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| D | qcom,gpucc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm graphics clock control module which supports the clocks, resets and
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
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| D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | qcom,sc7280-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm LPASS core and audio clock control module provides the clocks and
17 include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
18 include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
23 clock-names: true
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| D | qcom,gpucc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm graphics clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,gpucc-sdm845.h
18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h
19 include/dt-bindings/clock/qcom,gpucc-sc7180.h
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| D | maxim,max77686.txt | 1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
3 This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4 multi-function device. More information can be found in MFD DT binding
6 bindings/mfd/max77686.txt for MAX77686 and
7 bindings/mfd/max77802.txt for MAX77802 and
8 bindings/mfd/max77620.txt for MAX77620.
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
12 dt-bindings/clock/maxim,max77686.h.
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
17 dt-bindings/clock/maxim,max77802.h.
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| D | artpec6.txt | 1 * Clock bindings for Axis ARTPEC-6 chip
3 The bindings are based on the clock provider binding in
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 ----------------
9 There are two external inputs to the main clock controller which should be
10 provided using the common clock bindings.
11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference clock (optional).
14 Main clock controller
15 ---------------------
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| D | qcom,sc7180-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core Clock Controller on SC7180
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm LPASS core clock control module provides the clocks and power
16 See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
21 - qcom,sc7180-lpasshm
22 - qcom,sc7180-lpasscorecc
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| D | qcom,videocc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm video clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
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| D | st,stm32mp1-rcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32MP1 Reset Clock Controller
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
13 The RCC IP is both a reset and a clock controller.
17 This binding uses common clock bindings
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | sp810.txt | 2 -----------------------
6 - compatible: standard compatible string for a Primecell peripheral,
7 see Documentation/devicetree/bindings/arm/primecell.yaml
11 - reg: standard registers property, physical address and size
14 - clock-names: from the common clock bindings, for more details see
15 Documentation/devicetree/bindings/clock/clock-bindings.txt;
18 - clocks: from the common clock bindings, phandle and clock
19 specifier pairs for the entries of clock-names property
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,scu.txt | 2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
50 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
27 System controller Advanced Power Bus (APB) interface clock source.
29 clock-names:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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| D | composite.txt | 1 Binding for TI composite clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped composite clock with multiple different sub-types;
8 a multiplexer clock with multiple input clock signals or parents, one
11 an adjustable clock rate divider, this behaves exactly as [3]
14 clock, this behaves exactly as [4]
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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| D | composite.txt | 1 Binding for TI composite clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped composite clock with multiple different sub-types;
8 a multiplexer clock with multiple input clock signals or parents, one
11 an adjustable clock rate divider, this behaves exactly as [3]
14 clock, this behaves exactly as [4]
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen.txt | 30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
41 - reg : A Base address and length of the register set.
45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32";
49 clk_s_a0_pll: clk-s-a0-pll {
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen.txt | 30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
41 - reg : A Base address and length of the register set.
45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32";
49 clk_s_a0_pll: clk-s-a0-pll {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | ac100.txt | 1 X-Powers AC100 Codec/RTC IC Device Tree bindings
8 - compatible: "x-powers,ac100"
9 - reg: The I2C slave address or RSB hardware address for the chip
10 - sub-nodes:
11 - codec
12 - compatible: "x-powers,ac100-codec"
13 - interrupts: SoC NMI / GPIO interrupt connected to the
15 - #clock-cells: Shall be 0
16 - clock-output-names: "4M_adda"
18 - see clock/clock-bindings.txt for common clock bindings
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