Searched +full:clock +full:- +full:controller (Results 1 – 25 of 1160) sorted by relevance
12345678910>>...47
| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
55 Say Y if you want to support CPU clock scaling using CPUfreq
59 tristate "SDX55 and SDX65 APCS Clock Controller"
63 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
69 tristate "RPM based Clock Controller"
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
32 tristate "MSM8916 APCS Clock Controller"
35 Support for the APCS Clock Controller on msm8916 devices. The
41 tristate "MSM8996 CPU Clock Controller"
45 Support for the CPU clock controller on msm8996 devices.
46 Say Y if you want to support CPU clock scaling using CPUfreq
50 tristate "RPM based Clock Controller"
57 memory and accepts clock requests, aggregates the requests and turns
63 tristate "RPM over SMD based Clock Controller"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos5433-clock.txt | 1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
[all …]
|
| D | exynos5260-clock.txt | 1 * Samsung Exynos5260 Clock Controller
3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
[all …]
|
| D | exynos7-clock.txt | 1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
[all …]
|
| D | exynos4-clock.txt | 1 * Samsung Exynos4 Clock Controller
3 The Exynos4 clock controller generates and supplies clock to various controllers
4 within the Exynos4 SoC. The clock binding described here is applicable to all
9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume.
[all …]
|
| D | clk-exynos-audss.txt | 1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
4 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
9 - compatible: should be one of the following:
10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11 - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
13 - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
15 - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
17 - reg: physical base address and length of the controller's register set.
19 - #clock-cells: should be 1.
[all …]
|
| D | exynos3250-clock.txt | 1 * Samsung Exynos3250 Clock Controller
3 The Exynos3250 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
10 - "samsung,exynos3250-cmu-dmc" - controller compatible with
11 Exynos3250 SoC for Dynamic Memory Controller domain.
12 - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
20 Each clock is assigned an identifier and client nodes can use this identifier
[all …]
|
| D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
|
| D | samsung,s3c2443-clock.txt | 1 * Samsung S3C2443 Clock Controller
3 The S3C2443 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
[all …]
|
| D | samsung,s3c2410-clock.txt | 1 * Samsung S3C2410 Clock Controller
3 The S3C2410 clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to the s3c2410,
9 - compatible: should be one of the following.
10 - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
11 - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
12 - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
[all …]
|
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
[all …]
|
| D | exynos5420-clock.txt | 1 * Samsung Exynos5420 Clock Controller
3 The Exynos5420 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
12 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
18 to specify the clock which they consume.
21 dt-bindings/clock/exynos5420.h header and can be used in device
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt8195-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
14 PLLs -->
15 dividers -->
17 -->
[all …]
|
| D | mediatek,mt8192-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
42 Support for the clock controller present on the Samsung
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
17 Build the driver for PX30 Clock Driver.
20 bool "Rockchip RV110x clock controller support"
24 Build the driver for RV110x Clock Driver.
27 bool "Rockchip RV1126 clock controller support"
31 Build the driver for RV1126 Clock Driver.
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
16 Build the driver for PX30 Clock Driver.
19 bool "Rockchip RV110x clock controller support"
22 Build the driver for RV110x Clock Driver.
25 bool "Rockchip RK3036 clock controller support"
28 Build the driver for RK3036 Clock Driver.
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/hisilicon/ |
| D | hisi-x5hd2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014 Linaro Ltd.
4 * Copyright (c) 2013-2014 HiSilicon Limited.
7 #include <dt-bindings/clock/hix5hd2-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
17 gic: interrupt-controller@f8a01000 {
18 compatible = "arm,cortex-a9-gic";
19 #interrupt-cells = <3>;
20 #address-cells = <0>;
[all …]
|
| D | hi3620.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | hisi-x5hd2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014 Linaro Ltd.
4 * Copyright (c) 2013-2014 Hisilicon Limited.
7 #include <dt-bindings/clock/hix5hd2-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
17 gic: interrupt-controller@f8a01000 {
18 compatible = "arm,cortex-a9-gic";
19 #interrupt-cells = <3>;
20 #address-cells = <0>;
[all …]
|
| D | hi3620.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 Hisilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
|
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/ |
| D | rcar_can.txt | 1 Renesas R-Car CAN controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
6 "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
7 "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
8 "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
9 "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
10 "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
11 "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
12 "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
[all …]
|
12345678910>>...47