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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/panel/
Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/panel/
Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +----------+-------------------------------------+----------+-------+
24 +----------#######################################----------+-------+
29 |<-------->#<-------+--------------------------->#<-------->|<----->|
34 +----------#######################################----------+-------+
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@st.com>
11 - Olivier Moysan <olivier.moysan@st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
Dat91-sama5d2_adc.txt4 - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
5 - reg: Should contain ADC registers location and length.
6 - interrupts: Should contain the IRQ line for the ADC.
7 - clocks: phandle to device clock.
8 - clock-names: Must be "adc_clk".
9 - vref-supply: Supply used as reference for conversions.
10 - vddana-supply: Supply for the adc device.
11 - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
12 - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
13 - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
/kernel/linux/linux-5.10/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
49 * - Newer DaVinci chips have a controller called McASP,
[all …]
/kernel/linux/linux-6.6/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
49 * - Newer DaVinci chips have a controller called McASP,
[all …]
/kernel/linux/linux-6.6/Documentation/sound/soc/
Ddai.rst15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
53 receive the audio data. Bit clock usually varies depending on sample rate
58 Common PCM operating modes:-
[all …]
/kernel/linux/linux-5.10/Documentation/sound/soc/
Ddai.rst15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
53 receive the audio data. Bit clock usually varies depending on sample rate
58 Common PCM operating modes:-
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dcirrus,cs42l43.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 - $ref: dai-common.yaml#
26 - cirrus,cs42l43
31 vdd-p-supply:
35 vdd-a-supply:
39 vdd-d-supply:
43 vdd-io-supply:
[all …]
Dmicrochip,sama7g5-pdmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-pdmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
17 - $ref: dai-common.yaml#
21 const: microchip,sama7g5-pdmc
26 "#sound-dai-cells":
34 - description: Peripheral Bus Clock
35 - description: Generic Clock
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
34 * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled
35 * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal
36 * clock.
37 * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half
38 * crystal clock.
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
48 * @clk: Clock frequency.
51 * @ts_clk: TS clock (KHz).
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
34 * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled
35 * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal
36 * clock.
37 * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half
38 * crystal clock.
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
48 * @clk: Clock frequency.
51 * @ts_clk: TS clock (KHz).
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
[all …]
/kernel/linux/linux-6.6/drivers/staging/greybus/
Daudio_apbridgea.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (c) 2015-2016 Google Inc.
8 * we can predefine several low-level attributes of the communication
11 * - there are two channels (i.e., stereo)
12 * - the low-level protocol is I2S as defined by Philips/NXP
13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
15 * - WCLK low for left channel; high for right channel
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
/kernel/linux/linux-5.10/drivers/staging/greybus/
Daudio_apbridgea.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (c) 2015-2016 Google Inc.
8 * we can predefine several low-level attributes of the communication
11 * - there are two channels (i.e., stereo)
12 * - the low-level protocol is I2S as defined by Philips/NXP
13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
15 * - WCLK low for left channel; high for right channel
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/nfc/
Dnfcmrvl.txt4 - compatible: Should be:
5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
6 - "marvell,nfc-i2c" for I2C devices
7 - "marvell,nfc-spi" for SPI devices
10 - pinctrl-names: Contains only one value - "default".
11 - pintctrl-0: Specifies the pin control groups used for this controller.
12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
[all …]
/kernel/linux/linux-5.10/include/sound/
Dsoc-dai.h1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/sound/soc-dai.h -- ALSA SoC Layer
5 * Copyright: 2005-2008 Wolfson Microelectronics. PLC.
40 * DAI Clock gating.
45 #define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */
46 #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
55 * - "normal" polarity means signal is available at rising edge of BCLK
56 * - "inverted" polarity means signal is available at falling edge of BCLK
59 * - I2S: frame consists of left then right channel data. Left channel starts
60 * with falling FSYNC edge, right channel starts with rising FSYNC edge.
[all …]
/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_sii164.c1 // SPDX-License-Identifier: GPL-2.0
79 * edge_select - Edge Select:
80 * 0 = Input data is falling edge latched (falling
81 * edge latched first in dual edge mode)
82 * 1 = Input data is rising edge latched (rising
83 * edge latched first in dual edge mode)
84 * bus_select - Input Bus Select:
85 * 0 = Input data bus is 12-bits wide
86 * 1 = Input data bus is 24-bits wide
87 * dual_edge_clk_select - Dual Edge Clock Select
[all …]
/kernel/linux/linux-6.6/drivers/staging/sm750fb/
Dddk750_sii164.c1 // SPDX-License-Identifier: GPL-2.0
79 * edge_select - Edge Select:
80 * 0 = Input data is falling edge latched (falling
81 * edge latched first in dual edge mode)
82 * 1 = Input data is rising edge latched (rising
83 * edge latched first in dual edge mode)
84 * bus_select - Input Bus Select:
85 * 0 = Input data bus is 12-bits wide
86 * 1 = Input data bus is 24-bits wide
87 * dual_edge_clk_select - Dual Edge Clock Select
[all …]
/kernel/linux/linux-5.10/drivers/atm/
Dnicstarmac.c1 // SPDX-License-Identifier: GPL-2.0
20 do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
32 /* Write Data To EEProm from SI line on rising edge of CLK */
33 /* Read Data From EEProm on falling edge of CLK */
37 #define CLK_HIGH 0x0004 /* Clock high */
38 #define CLK_LOW 0x0000 /* Clock low */
88 /* Clock to read from/write to the eeprom */
117 * This routine will clock the Read_Status_reg function into the X2520
137 /* Done sending instruction - now pull data off of bit 16, MSB first */
138 /* Data clocked out of eeprom on falling edge of clock */
[all …]
/kernel/linux/linux-6.6/drivers/atm/
Dnicstarmac.c1 // SPDX-License-Identifier: GPL-2.0
27 /* Write Data To EEProm from SI line on rising edge of CLK */
28 /* Read Data From EEProm on falling edge of CLK */
32 #define CLK_HIGH 0x0004 /* Clock high */
33 #define CLK_LOW 0x0000 /* Clock low */
83 /* Clock to read from/write to the eeprom */
112 * This routine will clock the Read_Status_reg function into the X2520
132 /* Done sending instruction - now pull data off of bit 16, MSB first */
133 /* Data clocked out of eeprom on falling edge of clock */
136 for (i = 7, j = 0; i >= 0; i--) {
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
40 #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
41 #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
40 #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
41 #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
[all …]

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