| /kernel/linux/linux-5.10/sound/pci/lola/ |
| D | lola_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
17 unsigned int freq; in lola_sample_rate_convert() local
21 case 0: freq = 48000; break; in lola_sample_rate_convert()
22 case 1: freq = 44100; break; in lola_sample_rate_convert()
23 case 2: freq = 32000; break; in lola_sample_rate_convert()
31 case (1 << 2): freq *= 2; break; in lola_sample_rate_convert()
32 case (2 << 2): freq *= 4; break; in lola_sample_rate_convert()
33 case (5 << 2): freq /= 2; break; in lola_sample_rate_convert()
34 case (6 << 2): freq /= 4; break; in lola_sample_rate_convert()
[all …]
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| /kernel/linux/linux-6.6/sound/pci/lola/ |
| D | lola_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
17 unsigned int freq; in lola_sample_rate_convert() local
21 case 0: freq = 48000; break; in lola_sample_rate_convert()
22 case 1: freq = 44100; break; in lola_sample_rate_convert()
23 case 2: freq = 32000; break; in lola_sample_rate_convert()
31 case (1 << 2): freq *= 2; break; in lola_sample_rate_convert()
32 case (2 << 2): freq *= 4; break; in lola_sample_rate_convert()
33 case (5 << 2): freq /= 2; break; in lola_sample_rate_convert()
34 case (6 << 2): freq /= 4; break; in lola_sample_rate_convert()
[all …]
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| /kernel/linux/linux-6.6/sound/drivers/vx/ |
| D | vx_uer.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 mutex_lock(&chip->lock); in vx_read_one_cbit()
53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
62 mutex_unlock(&chip->lock); in vx_read_one_cbit()
67 * vx_write_one_cbit - write one bit to UER config
74 mutex_lock(&chip->lock); in vx_write_one_cbit()
82 mutex_unlock(&chip->lock); in vx_write_one_cbit()
[all …]
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| /kernel/linux/linux-5.10/sound/drivers/vx/ |
| D | vx_uer.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 mutex_lock(&chip->lock); in vx_read_one_cbit()
53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
62 mutex_unlock(&chip->lock); in vx_read_one_cbit()
67 * vx_write_one_cbit - write one bit to UER config
74 mutex_lock(&chip->lock); in vx_write_one_cbit()
82 mutex_unlock(&chip->lock); in vx_write_one_cbit()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
15 Value type: <phandle> From common clock binding.
16 Definition: clock handle for XO clock and GPLL0 clock.
18 - clock-names
20 Value type: <string> From common clock binding.
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
| D | msm_gpu_trace.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 __entry->pid = pid;
23 __entry->id = id;
24 __entry->ringid = ringid;
25 __entry->nr_bos = nr_bos;
26 __entry->nr_cmds = nr_cmds
29 __entry->id, __entry->pid, __entry->ringid,
30 __entry->nr_bos, __entry->nr_cmds)
44 __entry->pid = pid_nr(submit->pid);
45 __entry->id = submit->ident;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
[all …]
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| /kernel/linux/linux-5.10/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
36 { .compatible = "fsl,mpc5200-cdm", },
46 unsigned int freq; in mpc52xx_can_get_clock() local
52 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock()
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
54 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
65 if (!freq) in mpc52xx_can_get_clock()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
38 { .compatible = "fsl,mpc5200-cdm", },
48 unsigned int freq; in mpc52xx_can_get_clock() local
54 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock()
55 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
56 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock()
66 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
67 if (!freq) in mpc52xx_can_get_clock()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/ |
| D | msm_gpu_trace.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 __entry->pid = pid;
23 __entry->id = id;
24 __entry->ringid = ringid;
25 __entry->nr_bos = nr_bos;
26 __entry->nr_cmds = nr_cmds
29 __entry->id, __entry->pid, __entry->ringid,
30 __entry->nr_bos, __entry->nr_cmds)
44 __entry->pid = pid_nr(submit->pid);
45 __entry->id = submit->ident;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm845-cpufreq-hw
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_afmt.c | 34 /* Clock N CTS N CTS N CTS */
51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
57 n = 128 * freq; in amdgpu_afmt_calc_cts()
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts()
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts()
78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is disabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event()
[all …]
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_afmt.c | 34 /* Clock N CTS N CTS N CTS */
51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
57 n = 128 * freq; in amdgpu_afmt_calc_cts()
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts()
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts()
78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | atmel,sama5d2-pdmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-pdmic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
20 const: atmel,sama5d2-pdmic
30 - description: peripheral clock
31 - description: generated clock
33 clock-names:
35 - const: pclk
[all …]
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| /kernel/linux/linux-5.10/drivers/sh/clk/ |
| D | core.c | 2 * SuperH clock framework
4 * Copyright (C) 2005 - 2010 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2008 Nokia Corporation
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #define pr_fmt(fmt) "clock: " fmt
36 /* clock disable operations are not passed on to hardware during boot */
46 unsigned long freq; in clk_rate_table_build() local
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
[all …]
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| /kernel/linux/linux-6.6/drivers/sh/clk/ |
| D | core.c | 2 * SuperH clock framework
4 * Copyright (C) 2005 - 2010 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2008 Nokia Corporation
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #define pr_fmt(fmt) "clock: " fmt
36 /* clock disable operations are not passed on to hardware during boot */
46 unsigned long freq; in clk_rate_table_build() local
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | atmel-pdmic.txt | 4 - compatible
5 Should be "atmel,sama5d2-pdmic".
6 - reg
8 - interrupts
10 - dmas
11 One DMA specifiers as described in atmel-dma.txt and dma.txt files.
12 - dma-names
14 - clock-names
16 - "pclk" peripheral clock
17 - "gclk" generated clock
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ti/ |
| D | fapll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
13 #include "clock.h"
43 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
73 void __iomem *freq; member
81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass()
93 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass()
97 writel_relaxed(v, fd->base); in ti_fapll_set_bypass()
[all …]
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | armada-8k-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0+
34 unsigned int freq[ARRAY_SIZE(opps_div)]; member
37 /* If the CPUs share the same clock, then they are in the same cluster. */
55 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus()
70 unsigned int freq; in armada_8k_add_opp() local
76 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp()
77 return -EINVAL; in armada_8k_add_opp()
83 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp()
85 ret = dev_pm_opp_add(cpu_dev, freq, 0); in armada_8k_add_opp()
89 freq_tables[opps_index].freq[i] = freq; in armada_8k_add_opp()
[all …]
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| D | s3c24xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
62 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
63 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
64 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); in s3c_cpufreq_getcur()
65 cfg->freq.armclk = armclk = clk_get_rate(clk_arm); in s3c_cpufreq_getcur()
67 cfg->pll.driver_data = s3c24xx_read_mpllcon(); in s3c_cpufreq_getcur()
68 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
[all …]
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| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | armada-8k-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0+
25 { .compatible = "marvell,ap806-cpu-clock" },
26 { .compatible = "marvell,ap807-cpu-clock" },
41 unsigned int freq[ARRAY_SIZE(opps_div)]; member
44 /* If the CPUs share the same clock, then they are in the same cluster. */
62 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus()
77 unsigned int freq; in armada_8k_add_opp() local
83 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp()
84 return -EINVAL; in armada_8k_add_opp()
90 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_clock_utils.c | 1 // SPDX-License-Identifier: MIT
59 u32 freq = 0; in gen11_read_clock_frequency() local
62 * Note that on gen11+, the clock frequency may be reconfigured. in gen11_read_clock_frequency()
71 freq = read_reference_ts_freq(uncore); in gen11_read_clock_frequency()
75 freq = gen11_get_crystal_clock_freq(uncore, c0); in gen11_read_clock_frequency()
80 * increment only every few clock cycle). in gen11_read_clock_frequency()
82 freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> in gen11_read_clock_frequency()
86 return freq; in gen11_read_clock_frequency()
92 u32 freq = 0; in gen9_read_clock_frequency() local
95 freq = read_reference_ts_freq(uncore); in gen9_read_clock_frequency()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | vexpress-v2p-ca5s.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
|