Searched +full:clock +full:- +full:lanes (Results 1 – 25 of 1012) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | qcom,sm8250-camss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
18 const: qcom,sm8250-camss
24 clock-names:
26 - const: cam_ahb_clk
27 - const: cam_hf_axi
28 - const: cam_sf_axi
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| D | ti,cal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
15 processing capability to connect CSI2 image-sensor modules to the
24 - ti,dra72-cal
26 - ti,dra72-pre-es2-cal
28 - ti,dra76-cal
30 - ti,am654-cal
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| D | cdns,csi2rx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MIPI-CSI2 RX controller
10 - Maxime Ripard <mripard@kernel.org>
13 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
14 lanes in input, and 4 different pixel streams in output.
19 - enum:
20 - starfive,jh7110-csi2rx
21 - const: cdns,csi2rx
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| D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/renesas/ |
| D | r8a779a0-falcon-csi-dsi.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
23 remote-endpoint = <&max96712_out0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
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| D | hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "aistarvision-mipi-adapter-2.1.dtsi"
18 clock-lanes = <0>;
19 data-lanes = <1 2>;
20 remote-endpoint = <&ov5645_ep>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
34 remote-endpoint = <&imx219_ep>;
41 pinctrl-0 = <&i2c3_pins>;
42 pinctrl-names = "default";
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| D | r8a779g0-white-hawk-csi-dsi.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
24 remote-endpoint = <&max96712_out0>;
34 #address-cells = <1>;
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| D | r8a774c0-ek874-mipi-2.1.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774c0-ek874.dts"
13 #include "aistarvision-mipi-adapter-2.1.dtsi"
16 …model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-ada…
17 compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
38 clock-lanes = <0>;
39 data-lanes = <1 2>;
40 remote-endpoint = <&ov5645_ep>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.txt | 2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
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| D | nvidia,tegra124-xusb-padctl.txt | 4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
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| D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | ti,cal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
15 processing capability to connect CSI2 image-sensor modules to the
21 Documentation/devicetree/bindings/media/video-interfaces.txt.
27 - ti,dra72-cal
29 - ti,dra72-pre-es2-cal
31 - ti,dra76-cal
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| D | samsung-mipi-csis.txt | 1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
2 -------------------------------------------------------------
6 - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
7 "samsung,exynos4210-csis" for Exynos4210 (S5PC210),
8 "samsung,exynos4212-csis" for Exynos4212/Exynos4412,
9 "samsung,exynos5250-csis" for Exynos5250;
10 - reg : offset and length of the register set for the device;
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
13 - bus-width : maximum number of data lanes supported (SoC specific);
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | adv748x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kieran Bingham <kieran.bingham@ideasonboard.com>
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
15 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
21 - enum:
22 - adi,adv7481
23 - adi,adv7482
29 The ADV748x has up to twelve 256-byte maps that can be accessed via the
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| D | ovti,ov7251.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
15 - Todor Tomov <todor.too@gmail.com>
25 description: XCLK Input Clock
27 clock-names:
30 clock-frequency:
31 description: Frequency of the xclk clock in Hz.
33 vdda-supply:
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| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
10 source, the clock input is named "refclk".
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@xilinx.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
10 source, the clock input is named "refclk".
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
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| D | ov2680.txt | 1 * Omnivision OV2680 MIPI CSI-2 sensor
4 - compatible: should be "ovti,ov2680".
5 - clocks: reference to the xvclk input clock.
6 - clock-names: should be "xvclk".
7 - DOVDD-supply: Digital I/O voltage supply.
8 - DVDD-supply: Digital core voltage supply.
9 - AVDD-supply: Analog voltage supply.
12 - reset-gpios: reference to the GPIO connected to the powerdown/reset pin,
18 Documentation/devicetree/bindings/media/video-interfaces.txt.
20 Endpoint node required properties for CSI-2 connection are:
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| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/ |
| D | r8a774c0-ek874-mipi-2.1.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774c0-ek874.dts"
12 #include "aistarvision-mipi-adapter-2.1.dtsi"
15 …model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-ada…
16 compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
37 clock-lanes = <0>;
38 data-lanes = <1 2>;
39 remote-endpoint = <&ov5645_ep>;
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| /kernel/linux/linux-5.10/drivers/staging/media/rkisp1/Documentation/devicetree/bindings/media/ |
| D | rockchip-isp1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
18 const: rockchip,rk3399-cif-isp
29 power-domains:
36 phy-names:
41 - description: ISP clock
42 - description: ISP AXI clock clock
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| /kernel/linux/linux-6.6/drivers/gpu/drm/tegra/ |
| D | dp.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright (C) 2013-2019 NVIDIA Corporation
17 caps->enhanced_framing = false; in drm_dp_link_caps_reset()
18 caps->tps3_supported = false; in drm_dp_link_caps_reset()
19 caps->fast_training = false; in drm_dp_link_caps_reset()
20 caps->channel_coding = false; in drm_dp_link_caps_reset()
21 caps->alternate_scrambler_reset = false; in drm_dp_link_caps_reset()
27 dest->enhanced_framing = src->enhanced_framing; in drm_dp_link_caps_copy()
28 dest->tps3_supported = src->tps3_supported; in drm_dp_link_caps_copy()
29 dest->fast_training = src->fast_training; in drm_dp_link_caps_copy()
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