| /kernel/linux/linux-6.6/include/linux/ |
| D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
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| /kernel/linux/linux-5.10/include/linux/ |
| D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
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| /kernel/linux/linux-5.10/drivers/clk/zynqmp/ |
| D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
49 * @name: Parent name
50 * @id: Parent clock ID
54 char name[MAX_NAME_LEN]; member
60 * struct zynqmp_clock - Clock
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| /kernel/linux/linux-6.6/drivers/clk/zynqmp/ |
| D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
50 * @name: Parent name
51 * @id: Parent clock ID
55 char name[MAX_NAME_LEN]; member
61 * struct zynqmp_clock - Clock
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Common Clock Framework support for all Samsung platforms
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
17 * struct samsung_clk_provider: information about clock provider
19 * @dev: clock provider device needed for runtime PM.
20 * @lock: maintains exclusion between callbacks for a given clock-provider.
21 * @clk_data: holds clock related data like clk_hw* and number of clocks.
32 * struct samsung_clock_alias: information about mux clock
33 * @id: platform specific id of the clock.
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Common Clock Framework support for all Samsung platforms
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
17 * struct samsung_clk_provider: information about clock provider
19 * @lock: maintains exclusion between callbacks for a given clock-provider.
20 * @clk_data: holds clock related data like clk_hw* and number of clocks.
31 * struct samsung_clock_alias: information about mux clock
32 * @id: platform specific id of the clock.
33 * @dev_name: name of the device to which this clock belongs.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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| /kernel/linux/linux-6.6/drivers/clk/uniphier/ |
| D | clk-uniphier-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
13 #include "clk-uniphier.h"
19 switch (data->type) { in uniphier_clk_register()
21 return uniphier_clk_register_cpugear(dev, regmap, data->name, in uniphier_clk_register()
22 &data->data.cpugear); in uniphier_clk_register()
24 return uniphier_clk_register_fixed_factor(dev, data->name, in uniphier_clk_register()
25 &data->data.factor); in uniphier_clk_register()
27 return uniphier_clk_register_fixed_rate(dev, data->name, in uniphier_clk_register()
28 &data->data.rate); in uniphier_clk_register()
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| /kernel/linux/linux-5.10/drivers/isdn/mISDN/ |
| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * A clock source registers using mISDN_register_clock:
8 * name = text string to name clock source
9 * priority = value to priorize clock sources (0 = default)
10 * ctl = callback function to enable/disable clock source
11 * priv = private pointer of clock source
12 * return = pointer to clock source structure;
17 * A clock source calls mISDN_clock_update with given samples elapsed, if
21 * A clock source unregisters using mISDN_unregister_clock.
23 * To get current clock, call mISDN_clock_get. The signed short value
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| /kernel/linux/linux-6.6/drivers/isdn/mISDN/ |
| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * A clock source registers using mISDN_register_clock:
8 * name = text string to name clock source
9 * priority = value to priorize clock sources (0 = default)
10 * ctl = callback function to enable/disable clock source
11 * priv = private pointer of clock source
12 * return = pointer to clock source structure;
17 * A clock source calls mISDN_clock_update with given samples elapsed, if
21 * A clock source unregisters using mISDN_unregister_clock.
23 * To get current clock, call mISDN_clock_get. The signed short value
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/ |
| D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
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| D | exynos4210-trats.dts | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
37 stdout-path = "serial2:115200n8";
40 vemmc_reg: regulator-0 {
41 compatible = "regulator-fixed";
42 regulator-name = "VMEM_VDD_2.8V";
43 regulator-min-microvolt = <2800000>;
44 regulator-max-microvolt = <2800000>;
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| D | exynos4210-universal_c210.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
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| D | exynos4210-i9100.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
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| D | exynos4210-trats.dts | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
30 stdout-path = "serial2:115200n8";
33 vemmc_reg: regulator-0 {
34 compatible = "regulator-fixed";
35 regulator-name = "VMEM_VDD_2.8V";
36 regulator-min-microvolt = <2800000>;
37 regulator-max-microvolt = <2800000>;
39 enable-active-high;
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| D | exynos4210-universal_c210.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
28 stdout-path = "serial2:115200n8";
32 fixed-rate-clocks {
34 compatible = "samsung,clock-xxti";
35 clock-frequency = <0>;
39 compatible = "samsung,clock-xusbxti";
40 clock-frequency = <24000000>;
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| /kernel/linux/linux-5.10/drivers/clk/uniphier/ |
| D | clk-uniphier-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
14 #include "clk-uniphier.h"
20 switch (data->type) { in uniphier_clk_register()
22 return uniphier_clk_register_cpugear(dev, regmap, data->name, in uniphier_clk_register()
23 &data->data.cpugear); in uniphier_clk_register()
25 return uniphier_clk_register_fixed_factor(dev, data->name, in uniphier_clk_register()
26 &data->data.factor); in uniphier_clk_register()
28 return uniphier_clk_register_fixed_rate(dev, data->name, in uniphier_clk_register()
29 &data->data.rate); in uniphier_clk_register()
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | clk-mstp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25 * status register when enabling the clock.
31 * struct mstp_clock_group - MSTP gating clocks group
33 * @data: clock specifier translation for clocks in this group
37 * @width_8bit: registers are 8-bit, not 32-bit
50 * struct mstp_clock - MSTP gating clock
51 * @hw: handle between common and hardware-specific interfaces
66 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
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| /kernel/linux/linux-6.6/drivers/clk/renesas/ |
| D | clk-mstp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
26 * status register when enabling the clock.
32 * struct mstp_clock_group - MSTP gating clocks group
34 * @data: clock specifier translation for clocks in this group
38 * @width_8bit: registers are 8-bit, not 32-bit
51 * struct mstp_clock - MSTP gating clock
52 * @hw: handle between common and hardware-specific interfaces
67 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
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| /kernel/linux/linux-6.6/drivers/clk/ti/ |
| D | adpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
177 const char *name; in ti_adpll_clk_get_name() local
181 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
182 "clock-output-names", in ti_adpll_clk_get_name()
184 &name); in ti_adpll_clk_get_name()
188 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
189 d->pa, postfix); in ti_adpll_clk_get_name()
192 return name; in ti_adpll_clk_get_name()
197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
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| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI clock support
7 * Tero Kristo <t-kristo@ti.com>
11 #include <linux/clk-provider.h>
23 #include "clock.h"
43 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
45 if (reg->ptr) in clk_memmap_writel()
46 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
47 else if (io->regmap) in clk_memmap_writel()
48 regmap_write(io->regmap, reg->offset, val); in clk_memmap_writel()
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | adpll.c | 14 #include <linux/clk-provider.h>
186 const char *name; in ti_adpll_clk_get_name() local
190 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
191 "clock-output-names", in ti_adpll_clk_get_name()
193 &name); in ti_adpll_clk_get_name()
197 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
198 d->pa, postfix); in ti_adpll_clk_get_name()
201 return name; in ti_adpll_clk_get_name()
206 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
207 int index, int output_index, const char *name, in ti_adpll_setup_clock() argument
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