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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-dw-mshc
19 - samsung,exynos4412-dw-mshc
20 - samsung,exynos5250-dw-mshc
21 - samsung,exynos5420-dw-mshc
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
27 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
29 /* Get our parent clock, it's the one that can adjust its rate */ in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
[all …]
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
29 /* Get our parent clock, it's the one that can adjust its rate */ in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
/kernel/linux/linux-6.6/drivers/clk/sunxi/
Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
/kernel/linux/linux-6.6/drivers/clk/meson/
Dclk-phase.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
[all …]
/kernel/linux/linux-5.10/drivers/clk/meson/
Dclk-phase.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
31 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
36 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
40 * cclkin: source clock of mmc controller in dw_mci_rk3288_set_ios()
41 * bus_hz: card interface clock generated by CLKGEN in dw_mci_rk3288_set_ios()
43 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
46 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
48 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
[all …]
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
79 /* Default settings for ZynqMP Clock Phases */
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
29 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
34 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
38 * cclkin: source clock of mmc controller in dw_mci_rk3288_set_ios()
39 * bus_hz: card interface clock generated by CLKGEN in dw_mci_rk3288_set_ios()
41 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
44 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
46 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
[all …]
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
48 /* Default settings for ZynqMP Clock Phases */
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_dccg.c35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
[all …]
/kernel/linux/linux-5.10/drivers/media/i2c/
Dsaa711x_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * saa711x - Philips SAA711x video decoder register specifications
10 /* Video Decoder - Frontend part */
16 /* Video Decoder - Decoder part */
56 /* Audio clock generator part */
112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
196 /* SAA7113 bit-masks */
230 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
242 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
[all …]
/kernel/linux/linux-6.6/drivers/media/i2c/
Dsaa711x_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * saa711x - Philips SAA711x video decoder register specifications
10 /* Video Decoder - Frontend part */
16 /* Video Decoder - Decoder part */
56 /* Audio clock generator part */
112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
196 /* SAA7113 bit-masks */
230 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
242 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-samsung.txt8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Drealtek,otto-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sander Vanheule <sander@svanheule.net>
14 prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
[all …]
/kernel/linux/linux-6.6/sound/soc/pxa/
Dmmp-sspa.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/sound/soc/pxa/mmp-sspa.h
24 #define SSPA_CTL_XPH (1 << 31) /* Read Phase */
28 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */
30 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */
35 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */
37 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */
51 #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */
52 #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */
55 #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */
[all …]
/kernel/linux/linux-5.10/sound/soc/pxa/
Dmmp-sspa.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/sound/soc/pxa/mmp-sspa.h
24 #define SSPA_CTL_XPH (1 << 31) /* Read Phase */
28 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */
30 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */
35 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */
37 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */
51 #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */
52 #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */
55 #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
10 ADF435x Reference Clock (CLKIN).
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
[all …]
/kernel/linux/linux-5.10/drivers/iio/frequency/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
/kernel/linux/linux-6.6/drivers/clk/rockchip/
Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
85 * The below calculation is based on the output clock from in rockchip_mmc_set_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
87 * the clock rate from its parent, namely the output clock in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
[all …]
/kernel/linux/linux-5.10/drivers/clk/rockchip/
Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
85 * The below calculation is based on the output clock from in rockchip_mmc_set_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
87 * the clock rate from its parent, namely the output clock in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
[all …]

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