Searched +full:clocking +full:- +full:wizard (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx clocking wizard10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>13 The clocking wizard is a soft ip clocking block of Xilinx versal. It20 - xlnx,clocking-wizard21 - xlnx,clocking-wizard-v5.222 - xlnx,clocking-wizard-v6.0[all …]
1 # SPDX-License-Identifier: GPL-2.021 tristate "Xilinx Clocking Wizard"25 Support for the Xilinx Clocking Wizard IP core clock generator.26 Adds support for clocking wizard and compatible.27 This driver supports the Xilinx clocking wizard programmable clock
1 // SPDX-License-Identifier: GPL-2.03 * Xilinx 'Clocking Wizard' driver5 * Copyright (C) 2013 - 2021 Xilinx14 #include <linux/clk-provider.h>56 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */72 #define div_mask(width) ((1 << (width)) - 1)85 * struct clk_wzrd - Clock wizard private data structure110 * struct clk_wzrd_divider - clock divider specific to clk_wzrd112 * @hw: handle between common and hardware-specific interfaces154 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate()[all …]
1 Binding for Xilinx Clocking Wizard IP Core6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt7 [2] Clocking Wizard Product Guide8 https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf11 - compatible: Must be 'xlnx,clocking-wizard'12 - reg: Base and size of the cores register space13 - clocks: Handle to input clock14 - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'15 - clock-output-names: Names for the output clocks18 - speed-grade: Speed grade of the device (valid values are 1..3)[all …]
1 # SPDX-License-Identifier: GPL-2.03 # Xilinx Clocking Wizard Driver7 tristate "Xilinx Clocking Wizard"10 Support for the Xilinx Clocking Wizard IP core clock generator.
1 // SPDX-License-Identifier: GPL-2.03 * Xilinx 'Clocking Wizard' driver5 * Copyright (C) 2013 - 2014 Xilinx12 #include <linux/clk-provider.h>80 if (clk_wzrd->suspended) in clk_wzrd_clk_notifier()83 if (ndata->clk == clk_wzrd->clk_in1) in clk_wzrd_clk_notifier()84 max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; in clk_wzrd_clk_notifier()85 else if (ndata->clk == clk_wzrd->axi_clk) in clk_wzrd_clk_notifier()92 if (ndata->new_rate > max) in clk_wzrd_clk_notifier()106 clk_disable_unprepare(clk_wzrd->axi_clk); in clk_wzrd_suspend()[all …]
1 # SPDX-License-Identifier: GPL-2.04 obj-y += media/5 obj-$(CONFIG_PRISM2_USB) += wlan-ng/6 obj-$(CONFIG_COMEDI) += comedi/7 obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/8 obj-$(CONFIG_RTL8192U) += rtl8192u/9 obj-$(CONFIG_RTL8192E) += rtl8192e/10 obj-$(CONFIG_RTL8723BS) += rtl8723bs/11 obj-$(CONFIG_R8712U) += rtl8712/12 obj-$(CONFIG_R8188EU) += rtl8188eu/[all …]
1 # SPDX-License-Identifier: GPL-2.027 source "drivers/staging/wlan-ng/Kconfig"47 source "drivers/staging/octeon-usb/Kconfig"79 source "drivers/staging/clocking-wizard/Kconfig"83 source "drivers/staging/fsl-dpaa2/Kconfig"95 source "drivers/staging/mt7621-pci/Kconfig"97 source "drivers/staging/mt7621-pci-phy/Kconfig"99 source "drivers/staging/mt7621-pinctrl/Kconfig"101 source "drivers/staging/mt7621-dma/Kconfig"103 source "drivers/staging/ralink-gdma/Kconfig"[all …]