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/kernel/linux/linux-6.6/drivers/crypto/cavium/nitrox/
Dnitrox_reqmgr.c1 // SPDX-License-Identifier: GPL-2.0
24 * 0x00 - Success
26 * 0x43 - ERR_GC_DATA_LEN_INVALID
28 * less than 16 bytes for AES-XTS and AES-CTS.
29 * 0x45 - ERR_GC_CTX_LEN_INVALID
31 * 0x4F - ERR_GC_DOCSIS_CIPHER_INVALID
33 * AES/DES-CBC mode encryption.
34 * 0x50 - ERR_GC_DOCSIS_OFFSET_INVALID
39 * 0x51 - ERR_GC_CRC32_INVALID_SELECTION
41 * 0x52 - ERR_GC_AES_CCM_FLAG_INVALID
[all …]
/kernel/linux/linux-5.10/drivers/crypto/cavium/nitrox/
Dnitrox_reqmgr.c1 // SPDX-License-Identifier: GPL-2.0
23 * 0x00 - Success
25 * 0x43 - ERR_GC_DATA_LEN_INVALID
27 * less than 16 bytes for AES-XTS and AES-CTS.
28 * 0x45 - ERR_GC_CTX_LEN_INVALID
30 * 0x4F - ERR_GC_DOCSIS_CIPHER_INVALID
32 * AES/DES-CBC mode encryption.
33 * 0x50 - ERR_GC_DOCSIS_OFFSET_INVALID
38 * 0x51 - ERR_GC_CRC32_INVALID_SELECTION
40 * 0x52 - ERR_GC_AES_CCM_FLAG_INVALID
[all …]
/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-iommu.h>
20 #include <linux/io-pgtable.h>
29 #include <linux/pci-ats.h>
34 #include "arm-smmu-v3.h"
44 "Disable MSI-based polling for CMD_SYNC completion.");
80 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
81 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
89 return smmu->page1 + offset - SZ_64K; in arm_smmu_page1_fixup()
91 return smmu->base + offset; in arm_smmu_page1_fixup()
[all …]
Darm-smmu-v3.h1 /* SPDX-License-Identifier: GPL-2.0-only */
88 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
169 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
170 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
173 #define Q_ENT(q, p) ((q)->base + \
174 Q_IDX(&((q)->llq), p) * \
175 (q)->ent_dwords)
185 #define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1)
306 #define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
369 #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
[all …]
/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
30 #include "arm-smmu-v3.h"
31 #include "../../dma-iommu.h"
32 #include "../../iommu-sva.h"
42 "Disable MSI-based polling for CMD_SYNC completion.");
84 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
85 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
94 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
[all …]
Darm-smmu-v3.h1 /* SPDX-License-Identifier: GPL-2.0-only */
94 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
175 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
176 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
179 #define Q_ENT(q, p) ((q)->base + \
180 Q_IDX(&((q)->llq), p) * \
181 (q)->ent_dwords)
312 #define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
382 #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
408 #define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/gce/
Dmt8186-gce.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
82 /* CMDQ: debug */
85 /* CMDQ: P7: debug */
348 /* CMDQ sw tokens
367 /* Notify normal CMDQ there are some secure task done
368 * MUST NOT CHANGE, this token sync with secure world
372 /* CMDQ use sw token */
386 * There are 15 32-bit GPR, 3 GPR form a set
387 * (64-bit for address, 32-bit for value)
388 * MUST NOT CHANGE, these tokens sync with MDP
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_cmdq.c1 // SPDX-License-Identifier: GPL-2.0-only
78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
101 BUFDESC_LCMD_LEN = 2, /* 16 bytes - 2(8 byte unit) */
102 BUFDESC_SCMD_LEN = 3, /* 24 bytes - 3(8 byte unit) */
106 CTRL_SECT_LEN = 1, /* 4 bytes (ctrl) - 1(8 byte unit) */
107 CTRL_DIRECT_SECT_LEN = 2, /* 12 bytes (ctrl + rsvd) - 2(8 byte unit) */
125 * hinic_alloc_cmdq_buf - alloc buffer for sending command
129 * Return 0 - Success, negative - Failure
134 struct hinic_hwif *hwif = cmdqs->hwif; in hinic_alloc_cmdq_buf()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_cmdq.c1 // SPDX-License-Identifier: GPL-2.0-only
78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
96 BUFDESC_LCMD_LEN = 2, /* 16 bytes - 2(8 byte unit) */
97 BUFDESC_SCMD_LEN = 3, /* 24 bytes - 3(8 byte unit) */
101 CTRL_SECT_LEN = 1, /* 4 bytes (ctrl) - 1(8 byte unit) */
102 CTRL_DIRECT_SECT_LEN = 2, /* 12 bytes (ctrl + rsvd) - 2(8 byte unit) */
120 * hinic_alloc_cmdq_buf - alloc buffer for sending command
124 * Return 0 - Success, negative - Failure
129 struct hinic_hwif *hwif = cmdqs->hwif; in hinic_alloc_cmdq_buf()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns3/hns3_common/
Dhclge_comm_cmd.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2021-2021 Hisilicon Limited.
10 dma_addr_t dma = ring->desc_dma_addr; in hclge_comm_cmd_config_regs()
13 if (ring->ring_type == HCLGE_COMM_TYPE_CSQ) { in hclge_comm_cmd_config_regs()
20 reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S; in hclge_comm_cmd_config_regs()
29 reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S; in hclge_comm_cmd_config_regs()
38 hclge_comm_cmd_config_regs(hw, &hw->cmq.csq); in hclge_comm_cmd_init_regs()
39 hclge_comm_cmd_config_regs(hw, &hw->cmq.crq); in hclge_comm_cmd_init_regs()
44 desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR | in hclge_comm_cmd_reuse_desc()
47 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR); in hclge_comm_cmd_reuse_desc()
[all …]
/kernel/linux/linux-5.10/drivers/infiniband/hw/bnxt_re/
Dqplib_rcfw.c2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
58 struct bnxt_qplib_cmdq_ctx *cmdq; in __wait_for_resp() local
62 cmdq = &rcfw->cmdq; in __wait_for_resp()
63 cbit = cookie % rcfw->cmdq_depth; in __wait_for_resp()
64 rc = wait_event_timeout(cmdq->waitq, in __wait_for_resp()
65 !test_bit(cbit, cmdq->cmdq_bitmap), in __wait_for_resp()
67 return rc ? 0 : -ETIMEDOUT; in __wait_for_resp()
73 struct bnxt_qplib_cmdq_ctx *cmdq; in __block_for_resp() local
76 cmdq = &rcfw->cmdq; in __block_for_resp()
[all …]
/kernel/linux/linux-6.6/drivers/infiniband/hw/bnxt_re/
Dqplib_rcfw.c2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
57 * bnxt_qplib_map_rc - map return type based on opcode
95 return -ETIMEDOUT; in bnxt_qplib_map_rc()
100 * bnxt_re_is_fw_stalled - Check firmware health
105 * rcfw->max_timeout, consider firmware as stalled.
109 * -ENODEV if firmware is not responding
114 struct bnxt_qplib_cmdq_ctx *cmdq; in bnxt_re_is_fw_stalled() local
117 crsqe = &rcfw->crsqe_tbl[cookie]; in bnxt_re_is_fw_stalled()
118 cmdq = &rcfw->cmdq; in bnxt_re_is_fw_stalled()
[all …]
/kernel/linux/linux-6.6/drivers/accel/ivpu/
Divpu_mmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
39 #define IVPU_MMU_Q_WRAP_MASK (IVPU_MMU_Q_WRAP_BIT - 1)
40 #define IVPU_MMU_Q_IDX_MASK (IVPU_MMU_Q_COUNT - 1)
189 #define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(VPU_37XX_HOST_MMU_GERROR, CMDQ)) | \
211 return "Transaction marks non-substream disabled"; in ivpu_mmu_event_to_str()
239 return "Unknown CMDQ command"; in ivpu_mmu_event_to_str()
279 struct ivpu_mmu_info *mmu = vdev->mmu; in ivpu_mmu_cdtab_alloc()
280 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab; in ivpu_mmu_cdtab_alloc()
283 cdtab->base = dmam_alloc_coherent(vdev->drm.dev, size, &cdtab->dma, GFP_KERNEL); in ivpu_mmu_cdtab_alloc()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/
Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/pcie/
Dtrans.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/pcie/
Dtrans.c8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
73 #include "iwl-drv.h"
74 #include "iwl-trans.h"
75 #include "iwl-csr.h"
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/hns3/hns3vf/
Dhclgevf_cmd.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
5 #include <linux/dma-direction.h>
6 #include <linux/dma-mapping.h>
14 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)
18 int ntc = ring->next_to_clean; in hclgevf_ring_space()
19 int ntu = ring->next_to_use; in hclgevf_ring_space()
22 used = (ntu - ntc + ring->desc_num) % ring->desc_num; in hclgevf_ring_space()
24 return ring->desc_num - used - 1; in hclgevf_ring_space()
30 int ntu = ring->next_to_use; in hclgevf_is_valid_csq_clean_head()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_cmd.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
9 #include <linux/dma-direction.h>
14 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)
18 int ntu = ring->next_to_use; in hclge_ring_space()
19 int ntc = ring->next_to_clean; in hclge_ring_space()
20 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; in hclge_ring_space()
22 return ring->desc_num - used - 1; in hclge_ring_space()
27 int ntu = ring->next_to_use; in is_valid_csq_clean_head()
[all …]
/kernel/linux/linux-6.6/drivers/scsi/aacraid/
Dcomminit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
59 const unsigned long fibsize = dev->max_fib_size; in aac_alloc_comm()
66 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) || in aac_alloc_comm()
67 (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) || in aac_alloc_comm()
68 (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3 && in aac_alloc_comm()
69 !dev->sa_firmware)) { in aac_alloc_comm()
71 (dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB) in aac_alloc_comm()
[all …]
/kernel/linux/linux-5.10/drivers/scsi/aacraid/
Dcomminit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
59 const unsigned long fibsize = dev->max_fib_size; in aac_alloc_comm()
66 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) || in aac_alloc_comm()
67 (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) || in aac_alloc_comm()
68 (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3 && in aac_alloc_comm()
69 !dev->sa_firmware)) { in aac_alloc_comm()
71 (dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB) in aac_alloc_comm()
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/goya/
Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
44 * - checks DMA pointer
45 * - WREG, MSG_PROT are not allowed.
[all …]
/kernel/linux/linux-5.10/drivers/acpi/arm64/
Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/dma-map-ops.h>
44 * iort_set_fwnode() - Create iort_fwnode and use it to register
61 return -ENOMEM; in iort_set_fwnode()
63 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
64 np->iort_node = iort_node; in iort_set_fwnode()
65 np->fwnode = fwnode; in iort_set_fwnode()
68 list_add_tail(&np->list, &iort_fwnode_list); in iort_set_fwnode()
75 * iort_get_fwnode() - Retrieve fwnode associated with an IORT node
77 * @node: IORT table node to be looked-up
[all …]

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