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Searched full:cmu_fsys (Results 1 – 21 of 21) sorted by relevance

/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi317 cmu_fsys: clock-controller@156e0000 { label
1640 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1641 <&cmu_fsys CLK_SCLK_USBDRD30>,
1642 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1643 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1652 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1653 <&cmu_fsys CLK_ACLK_USBDRD30>,
1654 <&cmu_fsys CLK_SCLK_USBDRD30>;
1666 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1667 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
[all …]
Dexynos5433-tm2-common.dtsi257 &cmu_fsys {
260 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
261 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
262 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
263 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
264 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
265 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
272 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
273 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
274 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi415 cmu_fsys: clock-controller@156e0000 { label
1746 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1747 <&cmu_fsys CLK_SCLK_USBDRD30>,
1748 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1749 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1758 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1759 <&cmu_fsys CLK_ACLK_USBDRD30>,
1760 <&cmu_fsys CLK_SCLK_USBDRD30>;
1772 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1773 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
[all …]
Dexynos5433-tm2-common.dtsi262 &cmu_fsys {
265 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
266 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
270 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
277 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
[all …]
Dexynos7885.dtsi243 cmu_fsys: clock-controller@13400000 { label
302 clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
303 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dsamsung,exynos-pcie.yaml104 clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos7885.c184 /* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
676 /* ---- CMU_FSYS ------------------------------------------------------------ */
678 /* Register Offset definitions for CMU_FSYS (0x13400000) */
705 /* List of parent clocks for Muxes in CMU_FSYS */
Dclk-exynos5260.h101 *Registers for CMU_FSYS
Dclk-exynos5260.c421 /* CMU_FSYS */
Dclk-exynos5433.c1964 * Register offset definitions for CMU_FSYS
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dexynos7885.h134 /* CMU_FSYS */
Dexynos5260-clk.h262 /* List Of Clocks For CMU_FSYS */
Dexynos5433.h508 /* CMU_FSYS */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos7885-clock.yaml103 - description: CMU_FSYS bus clock (from CMU_TOP)
Dsamsung,exynos5433-clock.yaml39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
248 cmu_fsys: clock-controller@156e0000 {
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dexynos5260-clk.h278 /* List Of Clocks For CMU_FSYS */
Dexynos5433.h518 /* CMU_FSYS */
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h101 *Registers for CMU_FSYS
Dclk-exynos5260.c406 /* CMU_FSYS */
Dclk-exynos5433.c1941 * Register offset definitions for CMU_FSYS