Home
last modified time | relevance | path

Searched full:cmu_mif (Results 1 – 22 of 22) sorted by relevance

/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433-tm2.dts25 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
34 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
39 <&cmu_mif CLK_ACLK_DISP_333>,
40 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
42 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
47 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
48 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
50 <&cmu_mif CLK_SCLK_DSD_DISP>;
Dexynos5433-tm2e.dts25 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
34 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
38 <&cmu_mif CLK_ACLK_DISP_333>,
39 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
41 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
46 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
47 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
Dexynos5433.dtsi281 <&cmu_mif CLK_SCLK_MFC_PLL>,
282 <&cmu_mif CLK_SCLK_BUS_PLL>;
294 cmu_mif: clock-controller@105b0000 { label
373 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
374 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
375 <&cmu_mif CLK_SCLK_DSD_DISP>,
376 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
377 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
378 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
379 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
[all …]
Dexynos5433-bus.dtsi84 clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
Dexynos5433-tm2-common.dtsi292 &cmu_mif {
293 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
294 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos5433-tm2.dts26 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
35 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
40 <&cmu_mif CLK_ACLK_DISP_333>,
41 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
43 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
48 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
49 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
51 <&cmu_mif CLK_SCLK_DSD_DISP>;
Dexynos5433-tm2e.dts26 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
35 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
39 <&cmu_mif CLK_ACLK_DISP_333>,
40 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
42 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
47 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
48 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
Dexynos5433.dtsi379 <&cmu_mif CLK_SCLK_MFC_PLL>,
380 <&cmu_mif CLK_SCLK_BUS_PLL>;
392 cmu_mif: clock-controller@105b0000 { label
471 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
472 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
473 <&cmu_mif CLK_SCLK_DSD_DISP>,
474 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
475 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
476 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
477 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
[all …]
Dexynos5433-bus.dtsi84 clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
Dexynos5433-tm2-common.dtsi297 &cmu_mif {
298 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
299 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
212 <&cmu_mif CLK_SCLK_MFC_PLL>,
213 <&cmu_mif CLK_SCLK_BUS_PLL>;
225 cmu_mif: clock-controller@105b0000 {
304 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
305 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
306 <&cmu_mif CLK_SCLK_DSD_DISP>,
307 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
308 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
309 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
522 <&cmu_mif CLK_SCLK_MFC_PLL>,
523 <&cmu_mif CLK_SCLK_BUS_PLL>;
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dexynos5260-clk.h168 /* List Of Clocks For CMU_MIF */
Dexynos5433.h201 /* CMU_MIF */
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dexynos5260-clk.h174 /* List Of Clocks For CMU_MIF */
Dexynos5433.h205 /* CMU_MIF */
/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos5260.h282 *Registers for CMU_MIF
Dclk-exynos5260.c1047 /* CMU_MIF */
Dclk-exynos5433.c918 * Register offset definitions for CMU_MIF
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h282 *Registers for CMU_MIF
Dclk-exynos5260.c1032 /* CMU_MIF */
Dclk-exynos5433.c895 * Register offset definitions for CMU_MIF