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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
[all …]
Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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Damlogic,g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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Dcalxeda-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
24 '#phy-cells':
36 - compatible
37 - reg
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
[all …]
Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-[0-9a-f])*$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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Damlogic,g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_combo_phy.c1 // SPDX-License-Identifier: MIT
17 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
33 .name = "0.85V dot0 (low-voltage)",
55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 enum phy phy) in icl_set_procmon_ref_values() argument
82 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
85 (0xff << 16) | 0xff, procmon->dw1); in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
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Dintel_dpll_mgr.h2 * Copyright © 2012-2016 Intel Corporation
42 * enum intel_dpll_id - possible DPLL ids
48 * @DPLL_ID_PRIVATE: non-shared dpll in use
50 DPLL_ID_PRIVATE = -1,
107 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
111 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
115 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
152 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
156 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
160 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_combo_phy.c1 // SPDX-License-Identifier: MIT
14 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
41 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in cnl_get_procmon_ref_values() argument
51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
77 enum phy phy) in cnl_set_procmon_ref_values() argument
82 procmon = cnl_get_procmon_ref_values(dev_priv, phy); in cnl_set_procmon_ref_values()
84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
86 val |= procmon->dw1; in cnl_set_procmon_ref_values()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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/kernel/linux/linux-6.6/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
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/kernel/linux/linux-5.10/drivers/phy/amlogic/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Amlogic platforms
6 tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver"
19 tristate "Meson GXL and GXM USB2 PHY drivers"
31 tristate "Meson G12A USB2 PHY driver"
42 tristate "Meson G12A USB3+PCIE Combo PHY driver"
48 Enable this to support the Meson USB3 + PCIE Combo PHY found
53 tristate "Meson AXG PCIE PHY driver"
59 Enable this to support the Meson MIPI + PCIE PHY found
64 tristate "Meson AXG MIPI + PCIE analog PHY driver"
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/kernel/linux/linux-6.6/drivers/phy/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
49 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
[all …]
/kernel/linux/linux-6.6/drivers/phy/amlogic/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Amlogic platforms
6 tristate "Meson8, Meson8b and Meson8m2 HDMI TX PHY driver"
16 tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver"
29 tristate "Meson GXL and GXM USB2 PHY drivers"
53 tristate "Meson G12A USB2 PHY driver"
64 tristate "Meson G12A USB3+PCIE Combo PHY driver"
70 Enable this to support the Meson USB3 + PCIE Combo PHY found
75 tristate "Meson AXG PCIE PHY driver"
81 Enable this to support the Meson MIPI + PCIE PHY found
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
25 compatible = "generic-xhci";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
25 compatible = "generic-xhci";
[all …]
/kernel/linux/linux-6.6/drivers/phy/intel/
Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
15 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
80 struct phy *phy; member
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) += phy-intel-keembay-emmc.o
3 obj-$(CONFIG_PHY_INTEL_KEEMBAY_USB) += phy-intel-keembay-usb.o
4 obj-$(CONFIG_PHY_INTEL_LGM_COMBO) += phy-intel-lgm-combo.o
5 obj-$(CONFIG_PHY_INTEL_LGM_EMMC) += phy-intel-lgm-emmc.o
/kernel/linux/linux-5.10/drivers/phy/intel/
Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
15 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
80 struct phy *phy; member
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) += phy-intel-keembay-emmc.o
3 obj-$(CONFIG_PHY_INTEL_LGM_COMBO) += phy-intel-lgm-combo.o
4 obj-$(CONFIG_PHY_INTEL_LGM_EMMC) += phy-intel-lgm-emmc.o
/kernel/linux/linux-6.6/drivers/phy/allwinner/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Allwinner platforms
6 tristate "Allwinner sunxi SoC USB PHY driver"
19 This driver controls the entire USB PHY block, both the USB OTG
23 tristate "Allwinner A31 MIPI D-PHY Support"
32 MIPI-DSI support. If M is selected, the module will be
36 tristate "Allwinner sun9i SoC USB PHY driver"
47 This driver controls each individual USB 2 host PHY.
50 tristate "Allwinner H6 SoC USB3 PHY driver"
56 Enable this to support the USB3.0-capable transceiver that is
[all …]
/kernel/linux/linux-5.10/drivers/phy/allwinner/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Allwinner platforms
6 tristate "Allwinner sunxi SoC USB PHY driver"
19 This driver controls the entire USB PHY block, both the USB OTG
23 tristate "Allwinner A31 MIPI D-PHY Support"
32 MIPI-DSI support. If M is selected, the module will be
36 tristate "Allwinner sun9i SoC USB PHY driver"
47 This driver controls each individual USB 2 host PHY.
50 tristate "Allwinner H6 SoC USB3 PHY driver"
56 Enable this to support the USB3.0-capable transceiver that is
[all …]

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