Searched +full:control +full:- +full:bit (Results 1 – 25 of 1119) sorted by relevance
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/analogix/ |
| D | analogix-i2c-dptx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #define SP_AUTH_FAIL BIT(5)
18 #define SP_AUTHEN_PASS BIT(1)
20 /* HDCP Control Register 0 */
22 #define SP_RX_REPEATER BIT(6)
23 #define SP_RE_AUTH BIT(5)
24 #define SP_SW_AUTH_OK BIT(4)
25 #define SP_HARD_AUTH_EN BIT(3)
26 #define SP_HDCP_ENC_EN BIT(2)
27 #define SP_BKSV_SRM_PASS BIT(1)
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| D | analogix-anx78xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include "analogix-i2c-dptx.h"
10 #include "analogix-i2c-txcommon.h"
17 * System Control and Status
22 #define SP_VIDEO_RST BIT(4)
23 #define SP_HDCP_MAN_RST BIT(2)
24 #define SP_TMDS_RST BIT(1)
25 #define SP_SW_MAN_RST BIT(0)
29 #define SP_TMDS_CLOCK_DET BIT(1)
30 #define SP_TMDS_DE_DET BIT(0)
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| D | analogix-i2c-txcommon.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
25 /* Power Down Control Register */
27 #define SP_REGISTER_PD BIT(7)
28 #define SP_HDCP_PD BIT(5)
29 #define SP_AUDIO_PD BIT(4)
30 #define SP_VIDEO_PD BIT(3)
31 #define SP_LINK_PD BIT(2)
32 #define SP_TOTAL_PD BIT(1)
34 /* Reset Control Register 1 */
36 #define SP_MISC_RST BIT(7)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/ |
| D | analogix-i2c-dptx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #define SP_AUTH_FAIL BIT(5)
18 #define SP_AUTHEN_PASS BIT(1)
20 /* HDCP Control Register 0 */
22 #define SP_RX_REPEATER BIT(6)
23 #define SP_RE_AUTH BIT(5)
24 #define SP_SW_AUTH_OK BIT(4)
25 #define SP_HARD_AUTH_EN BIT(3)
26 #define SP_HDCP_ENC_EN BIT(2)
27 #define SP_BKSV_SRM_PASS BIT(1)
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| D | analogix-anx78xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include "analogix-i2c-dptx.h"
10 #include "analogix-i2c-txcommon.h"
17 * System Control and Status
22 #define SP_VIDEO_RST BIT(4)
23 #define SP_HDCP_MAN_RST BIT(2)
24 #define SP_TMDS_RST BIT(1)
25 #define SP_SW_MAN_RST BIT(0)
29 #define SP_TMDS_CLOCK_DET BIT(1)
30 #define SP_TMDS_DE_DET BIT(0)
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| D | analogix-i2c-txcommon.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
25 /* Power Down Control Register */
27 #define SP_REGISTER_PD BIT(7)
28 #define SP_HDCP_PD BIT(5)
29 #define SP_AUDIO_PD BIT(4)
30 #define SP_VIDEO_PD BIT(3)
31 #define SP_LINK_PD BIT(2)
32 #define SP_TOTAL_PD BIT(1)
34 /* Reset Control Register 1 */
36 #define SP_MISC_RST BIT(7)
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-microchip-core.c | 1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
32 #define CONTROL_ENABLE BIT(0)
33 #define CONTROL_MASTER BIT(1)
34 #define CONTROL_RX_DATA_INT BIT(4)
35 #define CONTROL_TX_DATA_INT BIT(5)
36 #define CONTROL_RX_OVER_INT BIT(6)
37 #define CONTROL_TX_UNDER_INT BIT(7)
38 #define CONTROL_SPO BIT(24)
39 #define CONTROL_SPH BIT(25)
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| /kernel/linux/linux-6.6/sound/soc/ti/ |
| D | davinci-mcasp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
79 /* Serializer n Control Register */
100 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
103 #define MCASP_FREE BIT(0)
104 #define MCASP_SOFT BIT(1)
107 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
108 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
109 * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
110 * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
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| /kernel/linux/linux-5.10/sound/soc/ti/ |
| D | davinci-mcasp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
79 /* Serializer n Control Register */
100 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
103 #define MCASP_FREE BIT(0)
104 #define MCASP_SOFT BIT(1)
107 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
108 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
109 * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
110 * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
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| /kernel/linux/linux-5.10/arch/x86/kvm/svm/ |
| D | svm.h | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
98 /* cache for control fields of the guest */
128 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
130 * perform speculative control.
156 * Per-vcpu list of struct amd_svm_iommu_ir:
164 /* Save desired MSR intercept (read: pass-through) state */
198 vmcb->control.clean = 0; in vmcb_mark_all_dirty()
203 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) in vmcb_mark_all_clean()
207 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) in vmcb_mark_dirty() argument
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| /kernel/linux/linux-6.6/drivers/net/ethernet/ti/ |
| D | cpsw_sl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
30 CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */
31 CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */
32 CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */
33 CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
34 CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
35 CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */
36 CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */
37 CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/ti/ |
| D | cpsw_sl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
30 CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */
31 CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */
32 CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */
33 CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
34 CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
35 CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */
36 CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */
37 CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */
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| /kernel/linux/linux-5.10/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
22 * index of the lowest bit of the multiplier value in the PLL's
23 * control register)
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
28 * index of the lowest bit of the divider value in the PLL's
29 * control register)
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| /kernel/linux/linux-5.10/drivers/media/usb/stk1160/ |
| D | stk1160-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * <elezegarcia--a.t--gmail.com>
10 * <rmthomas--a.t--sciolus.org>
13 /* GPIO Control */
16 /* Remote Wakeup Control */
19 /* Power-on Strapping Data */
24 #define STK1160_POSV_L_ACDOUT BIT(3)
25 #define STK1160_POSV_L_ACSYNC BIT(2)
28 * Decoder Control Register:
30 * with bit #7 (0x?? OR 0x80 to activate).
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| /kernel/linux/linux-6.6/drivers/media/usb/stk1160/ |
| D | stk1160-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * <elezegarcia--a.t--gmail.com>
10 * <rmthomas--a.t--sciolus.org>
13 /* GPIO Control */
16 /* Remote Wakeup Control */
19 /* Power-on Strapping Data */
24 #define STK1160_POSV_L_ACDOUT BIT(3)
25 #define STK1160_POSV_L_ACSYNC BIT(2)
28 * Decoder Control Register:
30 * with bit #7 (0x?? OR 0x80 to activate).
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| /kernel/linux/linux-5.10/include/linux/mfd/da9052/ |
| D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 /* CONTROL REGISTERS */
59 /* POWER SEQUENCER CONTROL REGISTERS */
100 /* BATTERY CONTROL REGISTRS */
106 /* LED CONTROL REGISTERS */
119 /* ADC CONTROL REGISTERS */
148 /* TSI CONTROL REGISTERS */
164 /* RTC CONTROL REGISTERS */
175 /* PAGE CONFIGURATION BIT */
274 /* CONTROL REGISTER A BITS */
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| /kernel/linux/linux-6.6/include/linux/mfd/da9052/ |
| D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 /* CONTROL REGISTERS */
59 /* POWER SEQUENCER CONTROL REGISTERS */
100 /* BATTERY CONTROL REGISTRS */
106 /* LED CONTROL REGISTERS */
119 /* ADC CONTROL REGISTERS */
148 /* TSI CONTROL REGISTERS */
164 /* RTC CONTROL REGISTERS */
175 /* PAGE CONFIGURATION BIT */
274 /* CONTROL REGISTER A BITS */
[all …]
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| /kernel/linux/linux-6.6/drivers/net/dsa/b53/ |
| D | b53_regs.h | 5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
24 #define B53_CTRL_PAGE 0x00 /* Control */
28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
53 /* EEE Control Registers Page */
60 * Control Page registers
63 /* Port Control Register (8 bit) */
65 #define PORT_CTRL_RX_DISABLE BIT(0)
66 #define PORT_CTRL_TX_DISABLE BIT(1)
67 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
68 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
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| /kernel/linux/linux-5.10/drivers/net/dsa/b53/ |
| D | b53_regs.h | 5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
24 #define B53_CTRL_PAGE 0x00 /* Control */
28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
53 /* EEE Control Registers Page */
60 * Control Page registers
63 /* Port Control Register (8 bit) */
65 #define PORT_CTRL_RX_DISABLE BIT(0)
66 #define PORT_CTRL_TX_DISABLE BIT(1)
67 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
68 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
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| /kernel/linux/linux-6.6/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
22 * index of the lowest bit of the multiplier value in the PLL's
23 * control register)
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
28 * index of the lowest bit of the divider value in the PLL's
29 * control register)
[all …]
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| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_easrc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/platform_data/dma-imx.h>
20 /* ASRC Context Control */
22 /* ASRC Context Control Extended 1 */
24 /* ASRC Context Control Extended 2 */
26 /* ASRC Control Input Access */
28 /* ASRC Datapath Processor Control Slot0 */
33 /* ASRC Datapath Processor Control Slot1 */
38 /* ASRC Context Output Control */
40 /* ASRC Control Output Access */
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| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| D | fsl_easrc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma/imx-dma.h>
20 /* ASRC Context Control */
22 /* ASRC Context Control Extended 1 */
24 /* ASRC Context Control Extended 2 */
26 /* ASRC Control Input Access */
28 /* ASRC Datapath Processor Control Slot0 */
33 /* ASRC Datapath Processor Control Slot1 */
38 /* ASRC Context Output Control */
40 /* ASRC Control Output Access */
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| /kernel/linux/linux-6.6/drivers/staging/iio/frequency/ |
| D | ad9834.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2010-2011 Analog Devices Inc.
31 #define AD9834_REG_FREQ0 BIT(14)
32 #define AD9834_REG_FREQ1 BIT(15)
33 #define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
34 #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
36 /* Command Control Bits */
38 #define AD9834_B28 BIT(13)
39 #define AD9834_HLB BIT(12)
40 #define AD9834_FSEL BIT(11)
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| /kernel/linux/linux-5.10/drivers/staging/iio/frequency/ |
| D | ad9834.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2010-2011 Analog Devices Inc.
31 #define AD9834_REG_FREQ0 BIT(14)
32 #define AD9834_REG_FREQ1 BIT(15)
33 #define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
34 #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
36 /* Command Control Bits */
38 #define AD9834_B28 BIT(13)
39 #define AD9834_HLB BIT(12)
40 #define AD9834_FSEL BIT(11)
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| /kernel/linux/linux-6.6/drivers/net/phy/ |
| D | dp83848.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
17 #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
21 #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
22 #define DP83848_MICR_INTEN BIT(1) /* Interrupt Enable */
25 #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
26 #define DP83848_MISR_FHF_INT_EN BIT(1) /* False Carrier Counter */
27 #define DP83848_MISR_ANC_INT_EN BIT(2) /* Auto-negotiation complete */
28 #define DP83848_MISR_DUP_INT_EN BIT(3) /* Duplex Status */
29 #define DP83848_MISR_SPD_INT_EN BIT(4) /* Speed status */
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