Searched +full:controller +full:- +full:number (Results 1 – 25 of 1104) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
5 The current design of the Linux kernel uses a single large number
6 space where each separate IRQ source is assigned a different number.
7 This is simple when there is only one interrupt controller, but in
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
18 Here the interrupt number loose all kind of correspondence to
21 interrupt controller (i.e. the component actually fireing the
22 interrupt line to the CPU) nowadays this number is just a number.
24 For this reason we need a mechanism to separate controller-local
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6 Function number.
11 * Bits [15:8] are the Bus number.
12 * Bits [7:3] are the Device number.
13 * Bits [2:0] are the Function number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
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| D | ralink,rt3883-pci.txt | 1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6 Function number.
11 * Bits [15:8] are the Bus number.
12 * Bits [7:3] are the Device number.
13 * Bits [2:0] are the Function number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
[all …]
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| /kernel/linux/linux-6.6/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
5 The current design of the Linux kernel uses a single large number
6 space where each separate IRQ source is assigned a different number.
7 This is simple when there is only one interrupt controller, but in
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
18 Here the interrupt number loose all kind of correspondence to
21 interrupt controller (i.e. the component actually fireing the
22 interrupt line to the CPU) nowadays this number is just a number.
24 For this reason we need a mechanism to separate controller-local
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
46 /* pin banks of exynos5433 pin-controller - ALIVE */
48 /* Must start with EINTG banks, ordered by EINT group number. */
60 /* pin banks of exynos5433 pin-controller - AUD */
62 /* Must start with EINTG banks, ordered by EINT group number. */
67 /* pin banks of exynos5433 pin-controller - CPIF */
69 /* Must start with EINTG banks, ordered by EINT group number. */
[all …]
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
63 * Samsung GPIO controller groups all the available pins into banks. The pins
77 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
108 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
110 * @pctl_offset: starting offset of the pin-bank registers.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.txt | 3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
11 package balls is under the control of a separate pin controller HW block. Two
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
36 The number of ports implemented by each GPIO controller varies. The number of
37 implemented GPIOs within each port varies. GPIO registers within a controller
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
[all …]
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| D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
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| D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 By using a serial interface, the SIO controller significantly extend
14 the number of available GPIOs with a minimum number of additional
17 controller.
21 pattern: "^gpio@[0-9a-f]+$"
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| /kernel/linux/linux-6.6/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
66 /* Must start with EINTG banks, ordered by EINT group number. */
78 /* pin banks of exynos5433 pin-controller - AUD */
80 /* Must start with EINTG banks, ordered by EINT group number. */
85 /* pin banks of exynos5433 pin-controller - CPIF */
[all …]
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| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
71 * Samsung GPIO controller groups all the available pins into banks. The pins
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
118 * @pctl_offset: starting offset of the pin-bank registers.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
[all …]
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| D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
[all …]
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| D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
17 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
27 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
36 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
45 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
54 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
59 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
63 …_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the to…
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/ |
| D | samsung-keypad.txt | 1 * Samsung's Keypad Controller device tree bindings
3 Samsung's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
10 - compatible: should be one of the following
11 - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
12 controller.
13 - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
14 controller.
16 - reg: physical base address of the controller and length of memory mapped
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | samsung-keypad.txt | 1 * Samsung's Keypad Controller device tree bindings
3 Samsung's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
10 - compatible: should be one of the following
11 - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
12 controller.
13 - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
14 controller.
16 - reg: physical base address of the controller and length of memory mapped
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | samsung,exynos4210-combiner.txt | 1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
11 is usually connected to a parent interrupt controller.
14 controller module (which includes multiple combiners). A combiner in the
15 interrupt controller module shares config/control registers with other
16 combiners. For example, a 32-bit interrupt enable/disable config register
21 - compatible: should be "samsung,exynos4210-combiner".
22 - interrupt-controller: Identifies the node as an interrupt controller.
[all …]
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| D | ti,omap2-intc.txt | 1 * OMAP Interrupt Controller
3 OMAP2/3 are using a TI interrupt controller that can support several
4 configurable number of interrupts.
8 - compatible : should be:
9 "ti,omap2-intc"
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
14 The cell contains the interrupt number in the range [0-128].
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
[all …]
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| D | ti,cp-intc.txt | 1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
4 OMAP-L1x SoCs and can support several configurable number
9 - compatible : should be:
10 "ti,cp-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
15 The cell contains the interrupt number in the range [0-128].
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,omap2-intc.txt | 1 * OMAP Interrupt Controller
3 OMAP2/3 are using a TI interrupt controller that can support several
4 configurable number of interrupts.
8 - compatible : should be:
9 "ti,omap2-intc"
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
14 The cell contains the interrupt number in the range [0-128].
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
[all …]
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| D | ti,cp-intc.txt | 1 * TI Common Platform Interrupt Controller
3 Common Platform Interrupt Controller (cp_intc) is used on
4 OMAP-L1x SoCs and can support several configurable number
9 - compatible : should be:
10 "ti,cp-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
15 The cell contains the interrupt number in the range [0-128].
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
[all …]
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| /kernel/linux/linux-5.10/include/linux/ |
| D | mhi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
10 #include <linux/dma-direction.h>
27 * enum mhi_callback - MHI callback
51 * enum mhi_flags - Transfer flags
63 * enum mhi_device_type - Device types
73 * enum mhi_ch_type - Channel types
89 * struct image_info - Firmware and RDDM table
102 * struct mhi_link_info - BW requirement
103 * target_link_speed - Link speed as defined by TLS bits in LinkControl reg
[all …]
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