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/kernel/linux/linux-5.10/drivers/clk/
Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
54 struct clk_core *core; member
100 #include <trace/events/clk.h>
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/kernel/linux/linux-6.6/drivers/clk/
Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
54 struct clk_core *core; member
100 #include <trace/events/clk.h>
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/kernel/linux/linux-6.6/drivers/clk/renesas/
Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
64 * struct clk_hw_data - clock hardware data
80 * struct sd_mux_hw_data - SD MUX clock hardware data
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Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
[all …]
Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
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Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
[all …]
Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
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/kernel/linux/linux-5.10/include/trace/events/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
17 TP_PROTO(struct clk_core *core),
19 TP_ARGS(core),
22 __string( name, core->name )
26 __assign_str(name, core->name);
32 DEFINE_EVENT(clk, clk_enable,
34 TP_PROTO(struct clk_core *core),
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/kernel/linux/linux-5.10/drivers/clk/microchip/
Dclk-pic32mzda.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/microchip,pic32-clock.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
17 #include "clk-core.h"
81 .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
128 struct clk *clks[MAXCLKS];
129 struct pic32_clk_common core; member
142 if (readl(cd->core.iobase) & BIT(2)) in pic32_fscm_nmi()
143 pr_alert("pic32-clk: FSCM detected clk failure.\n"); in pic32_fscm_nmi()
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Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
78 /* add instruction pipeline delay while CPU clock is in-transition. */
92 struct pic32_clk_common *core; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) in calc_best_divided_rate()
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/kernel/linux/linux-6.6/drivers/clk/microchip/
Dclk-pic32mzda.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/microchip,pic32-clock.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
17 #include "clk-core.h"
81 .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
128 struct clk *clks[MAXCLKS];
129 struct pic32_clk_common core; member
142 if (readl(cd->core.iobase) & BIT(2)) in pic32_fscm_nmi()
143 pr_alert("pic32-clk: FSCM detected clk failure.\n"); in pic32_fscm_nmi()
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Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
78 /* add instruction pipeline delay while CPU clock is in-transition. */
92 struct pic32_clk_common *core; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) in calc_best_divided_rate()
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/kernel/linux/linux-6.6/include/trace/events/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
17 TP_PROTO(struct clk_core *core),
19 TP_ARGS(core),
22 __string( name, core->name )
26 __assign_str(name, core->name);
32 DEFINE_EVENT(clk, clk_enable,
34 TP_PROTO(struct clk_core *core),
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/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/kernel/linux/linux-5.10/drivers/net/ipa/
Dipa_clock.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2020 Linaro Ltd.
9 #include <linux/clk.h>
20 * The "IPA Clock" manages both the IPA core clock and the interconnects
25 * disabled. We currently operate the core clock at a fixed clock rate, and
45 * struct ipa_clock - IPA clocking information
48 * @core: IPA core clock
56 struct clk *core; member
83 clock->memory_path = path; in ipa_interconnect_init()
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/kernel/linux/linux-5.10/drivers/clk/renesas/
Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
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Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
[all …]
Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Domap_hwmod_2xxx_interconnect_data.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
5 * Copyright (C) 2009-2011 Nokia Corporation
9 * XXX these should be marked initdata for multi-OMAP kernels
23 /* L3 -> L4_CORE interface */
30 /* MPU -> L3 interface */
37 /* DSS -> l3 */
50 /* L4_CORE -> L4_WKUP interface */
57 /* L4 CORE -> UART1 interface */
61 .clk = "uart1_ick",
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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap_hwmod_2xxx_interconnect_data.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
5 * Copyright (C) 2009-2011 Nokia Corporation
9 * XXX these should be marked initdata for multi-OMAP kernels
24 /* L3 -> L4_CORE interface */
31 /* MPU -> L3 interface */
38 /* DSS -> l3 */
51 /* L4_CORE -> L4_WKUP interface */
58 /* L4 CORE -> UART1 interface */
62 .clk = "uart1_ick",
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/kernel/linux/linux-5.10/arch/mips/lantiq/falcon/
Dsysctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "../clk.h"
80 static inline void sysctl_wait(struct clk *clk, in sysctl_wait() argument
85 do {} while (--err && ((sysctl_r32(clk->module, reg) in sysctl_wait()
86 & clk->bits) != test)); in sysctl_wait()
89 clk->module, clk->bits, test, in sysctl_wait()
90 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait()
93 static int sysctl_activate(struct clk *clk) in sysctl_activate() argument
95 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate()
96 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate()
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/kernel/linux/linux-6.6/arch/mips/lantiq/falcon/
Dsysctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "../clk.h"
80 static inline void sysctl_wait(struct clk *clk, in sysctl_wait() argument
85 do {} while (--err && ((sysctl_r32(clk->module, reg) in sysctl_wait()
86 & clk->bits) != test)); in sysctl_wait()
89 clk->module, clk->bits, test, in sysctl_wait()
90 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait()
93 static int sysctl_activate(struct clk *clk) in sysctl_activate() argument
95 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate()
96 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate()
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