Searched +full:cortex +full:- +full:a53 (Results 1 – 25 of 264) sorted by relevance
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt6755.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt6755.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
35 enable-method = "psci";
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| D | mt6795.dtsi | 14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
29 #address-cells = <1>;
30 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
35 enable-method = "psci";
[all …]
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| /kernel/linux/linux-6.6/Documentation/translations/zh_TW/arch/arm64/ |
| D | silicon-errata.txt | 1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
69 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
[all …]
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| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 1 Chinese translated version of Documentation/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
[all …]
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| /kernel/linux/linux-6.6/Documentation/translations/zh_CN/arch/arm64/ |
| D | silicon-errata.txt | 1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/realtek/ |
| D | rtd1295.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
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| D | rtd1296.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2017-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
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| D | rtd1395.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
40 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/realtek/ |
| D | rtd1296.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2017-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
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| D | rtd1295.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
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| D | rtd1395.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
40 compatible = "arm,cortex-a53";
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | s32g2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
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| D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amlogic/ |
| D | amlogic-t7.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <0x2>;
15 #size-cells = <0x0>;
17 cpu-map {
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
[all …]
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| D | meson-g12a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/ |
| D | exynos7885.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
34 interrupt-affinity = <&cpu0>,
42 arm-a73-pmu {
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/ |
| D | k3-am62a7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-g12a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/synaptics/ |
| D | as370.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-1.0";
22 #address-cells = <1>;
23 #size-cells = <0>;
26 compatible = "arm,cortex-a53";
29 enable-method = "psci";
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/ |
| D | mapfile.csv | 10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,core
18 0x00000000410fd040,v1,arm/cortex-a35,core
19 0x00000000410fd050,v1,arm/cortex-a55,core
20 0x00000000410fd060,v1,arm/cortex-a65-e1,core
21 0x00000000410fd4a0,v1,arm/cortex-a65-e1,core
22 0x00000000410fd070,v1,arm/cortex-a57-a72,core
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | mapfile.csv | 10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd030,v1,arm/cortex-a53,core
16 0x00000000420f1000,v1,arm/cortex-a53,core
17 0x00000000410fd070,v1,arm/cortex-a57-a72,core
18 0x00000000410fd080,v1,arm/cortex-a57-a72,core
19 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
20 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
[all …]
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
[all …]
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