| /kernel/linux/linux-6.6/arch/mips/kernel/ |
| D | cevt-bcm1480.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
33 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
34 void __iomem *cfg, *init; in sibyte_set_periodic() local
36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
37 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
39 __raw_writeq(0, cfg); in sibyte_set_periodic()
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
47 unsigned int cpu = smp_processor_id(); in sibyte_shutdown() local
48 void __iomem *cfg; in sibyte_shutdown() local
[all …]
|
| D | cevt-sb1250.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
31 void __iomem *cfg; in sibyte_shutdown() local
33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
36 __raw_writeq(0, cfg); in sibyte_shutdown()
43 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
44 void __iomem *cfg, *init; in sibyte_set_periodic() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
47 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | cevt-bcm1480.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
33 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
34 void __iomem *cfg, *init; in sibyte_set_periodic() local
36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
37 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
39 __raw_writeq(0, cfg); in sibyte_set_periodic()
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
47 unsigned int cpu = smp_processor_id(); in sibyte_shutdown() local
48 void __iomem *cfg; in sibyte_shutdown() local
[all …]
|
| D | cevt-sb1250.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
31 void __iomem *cfg; in sibyte_shutdown() local
33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
36 __raw_writeq(0, cfg); in sibyte_shutdown()
43 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
44 void __iomem *cfg, *init; in sibyte_set_periodic() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
47 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
[all …]
|
| /kernel/linux/linux-5.10/arch/ia64/kernel/ |
| D | irq_ia64.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Added CPU Hotplug handling for IPF.
58 static cpumask_t vector_allocation_domain(int cpu);
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
[all …]
|
| /kernel/linux/linux-6.6/arch/ia64/kernel/ |
| D | irq_ia64.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Added CPU Hotplug handling for IPF.
58 static cpumask_t vector_allocation_domain(int cpu);
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
[all …]
|
| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | s3c24xx-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
7 * S3C24XX CPU Frequency scaling
17 #include <linux/cpu.h>
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
58 static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) in s3c_cpufreq_getcur() argument
62 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
63 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
64 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); in s3c_cpufreq_getcur()
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/kernel/apic/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
26 static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg) in __irq_msi_compose_msg() argument
28 msg->address_hi = MSI_ADDR_BASE_HI; in __irq_msi_compose_msg()
31 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); in __irq_msi_compose_msg()
33 msg->address_lo = in __irq_msi_compose_msg()
35 ((apic->irq_dest_mode == 0) ? in __irq_msi_compose_msg()
39 MSI_ADDR_DEST_ID(cfg->dest_apicid); in __irq_msi_compose_msg()
41 msg->data = in __irq_msi_compose_msg()
45 MSI_DATA_VECTOR(cfg->vector); in __irq_msi_compose_msg()
53 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) in irq_msi_update_msg() argument
[all …]
|
| D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
33 * - Disabled on the command line in apic_smt_update()
34 * - Only a single CPU is online in apic_smt_update()
35 * - Not all present CPUs have been at least booted once in apic_smt_update()
55 apic->send_IPI_allbutself(vector); in apic_send_IPI_allbutself()
57 apic->send_IPI_mask_allbutself(cpu_online_mask, vector); in apic_send_IPI_allbutself()
61 * Send a 'reschedule' IPI to another CPU. It goes straight through and
65 void native_smp_send_reschedule(int cpu) in native_smp_send_reschedule() argument
67 if (unlikely(cpu_is_offline(cpu))) { in native_smp_send_reschedule()
68 WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu); in native_smp_send_reschedule()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
52 static struct omap_smp_config cfg; variable
71 return cfg.scu_base; in omap4_get_scu_base()
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", in omap5_erratum_workaround_801819()
139 pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n", in omap5_secondary_harden_predictor()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | omap-smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
52 static struct omap_smp_config cfg; variable
71 return cfg.scu_base; in omap4_get_scu_base()
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", in omap5_erratum_workaround_801819()
139 pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n", in omap5_secondary_harden_predictor()
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | hpet.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/cpu.h>
27 unsigned int cpu; member
132 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
142 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
150 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
152 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
209 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
211 switch (hc->mode) { in hpet_reserve_platform_timers()
214 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/loongson64/ |
| D | hpet.c | 1 // SPDX-License-Identifier: GPL-2.0
35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
[all …]
|
| /kernel/linux/linux-6.6/arch/mips/loongson64/ |
| D | hpet.c | 1 // SPDX-License-Identifier: GPL-2.0
35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/kernel/apic/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
26 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) in irq_msi_update_msg() argument
30 __irq_msi_compose_msg(cfg, msg, false); in irq_msi_update_msg()
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); in irq_msi_update_msg()
37 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd); in msi_set_affinity() local
38 struct irq_data *parent = irqd->parent_data; in msi_set_affinity()
39 unsigned int cpu; in msi_set_affinity() local
43 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd)); in msi_set_affinity()
44 old_cfg = *cfg; in msi_set_affinity()
47 ret = parent->chip->irq_set_affinity(parent, mask, force); in msi_set_affinity()
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/kernel/ |
| D | hpet.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/cpu.h>
28 unsigned int cpu; member
133 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
143 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
151 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
153 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
210 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
212 switch (hc->mode) { in hpet_reserve_platform_timers()
215 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/netlogic/xlr/ |
| D | fmn-config.c | 2 * Copyright (c) 2003-2012 Broadcom Corporation
35 #include <asm/cpu-info.h>
39 #include <asm/cpu.h>
70 fmn_info->credit_config[(bkt * 8) + 0], in print_credit_config()
71 fmn_info->credit_config[(bkt * 8) + 1], in print_credit_config()
72 fmn_info->credit_config[(bkt * 8) + 2], in print_credit_config()
73 fmn_info->credit_config[(bkt * 8) + 3], in print_credit_config()
74 fmn_info->credit_config[(bkt * 8) + 4], in print_credit_config()
75 fmn_info->credit_config[(bkt * 8) + 5], in print_credit_config()
76 fmn_info->credit_config[(bkt * 8) + 6], in print_credit_config()
[all …]
|
| /kernel/linux/linux-5.10/drivers/tty/ |
| D | mips_ejtag_fdc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
120 * @cpu: CPU number for this FDC.
123 * @ports: Per-channel data.
144 unsigned int cpu; member
174 __raw_writel(data, priv->reg + offs); in mips_ejtag_fdc_write()
180 return __raw_readl(priv->reg + offs); in mips_ejtag_fdc_read()
186 * struct fdc_word - FDC word encoding some number of bytes of data.
[all …]
|
| /kernel/linux/linux-6.6/drivers/tty/ |
| D | mips_ejtag_fdc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
120 * @cpu: CPU number for this FDC.
123 * @ports: Per-channel data.
144 unsigned int cpu; member
174 __raw_writel(data, priv->reg + offs); in mips_ejtag_fdc_write()
180 return __raw_readl(priv->reg + offs); in mips_ejtag_fdc_read()
186 * struct fdc_word - FDC word encoding some number of bytes of data.
[all …]
|
| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | hyperv-iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
18 #include <asm/cpu.h>
29 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
30 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
41 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
42 struct irq_cfg *cfg = irqd_cfg(data); in hyperv_ir_set_affinity() local
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
54 entry = data->chip_data; in hyperv_ir_set_affinity()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-s3c/ |
| D | init.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // S3C series CPU initialisation
26 #include "cpu.h"
29 static struct cpu_table *cpu; variable
35 for (; count != 0; count--, tab++) { in s3c_lookup_cpu()
36 if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) in s3c_lookup_cpu()
46 cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); in s3c_init_cpu()
48 if (cpu == NULL) { in s3c_init_cpu()
49 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); in s3c_init_cpu()
50 panic("Unknown S3C24XX CPU"); in s3c_init_cpu()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | init.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // S3C series CPU initialisation
26 #include "cpu.h"
29 static struct cpu_table *cpu; variable
35 for (; count != 0; count--, tab++) { in s3c_lookup_cpu()
36 if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) in s3c_lookup_cpu()
46 cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); in s3c_init_cpu()
48 if (cpu == NULL) { in s3c_init_cpu()
49 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); in s3c_init_cpu()
50 panic("Unknown S3C24XX CPU"); in s3c_init_cpu()
[all …]
|
| /kernel/linux/linux-6.6/tools/testing/selftests/bpf/map_tests/ |
| D | task_storage_map.c | 1 // SPDX-License-Identifier: GPL-2.0
33 while (!ctx->start) in lookup_fn()
36 while (!ctx->stop && i++ < ctx->loop) in lookup_fn()
37 bpf_map_lookup_elem(ctx->map_fd, &ctx->pid_fd, &value); in lookup_fn()
45 ctx->stop = true; in abort_lookup()
46 ctx->start = true; in abort_lookup()
54 unsigned int i, nr = 256, loop = 8192, cpu = 0; in test_task_storage_map_stress_lookup() local
59 const char *cfg; in test_task_storage_map_stress_lookup() local
62 cfg = getenv("TASK_STORAGE_MAP_NR_THREAD"); in test_task_storage_map_stress_lookup()
63 if (cfg) { in test_task_storage_map_stress_lookup()
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-cpu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * struct exynos_cpuclk_data: config data to setup cpu clocks.
19 * This structure holds the divider configuration data for dividers in the CPU
22 * For CPU clock domains that do not have a DIV1 register, the @div1 member
32 * struct exynos_cpuclk: information about clock supplied to a CPU core.
33 * @hw: handle between CCF and CPU clock.
37 * @lock: cpu clock domain register access lock.
38 * @cfg: cpu clock rate configuration data.
39 * @num_cfgs: number of array elements in @cfg array.
42 * @flags: configuration flags for the CPU clock.
[all …]
|
| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file contains the utility function to register CPU clock for Samsung
10 * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
11 * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
[all …]
|