Home
last modified time | relevance | path

Searched +full:cpu +full:- +full:intc (Results 1 – 25 of 638) sorted by relevance

12345678910>>...26

/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-bcm6345-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * ENABLE/STATUS words are packed next to each other for each CPU:
19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
[all …]
Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
83 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
86 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
89 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
92 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
95 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
98 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
101 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
104 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
125 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
[all …]
Dirq-bcm2836.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/cpu.h>
14 #include <linux/irqchip/irq-bcm2836.h>
23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
27 int cpu) in bcm2836_arm_irqchip_mask_per_cpu_irq() argument
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
36 int cpu) in bcm2836_arm_irqchip_unmask_per_cpu_irq() argument
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq()
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq()
[all …]
Dirq-hip04.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon HiP04 INTC
5 * Copyright (C) 2002-2014 ARM Limited.
6 * Copyright (c) 2013-2014 Hisilicon Ltd.
7 * Copyright (c) 2013-2014 Linaro Ltd.
9 * Interrupt architecture for the HIP04 INTC:
14 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * associated CPU. The base address of the CPU interface is usually
18 * on the CPU it is accessed from.
20 * Note that IRQs 0-31 are special - they are local to each CPU.
[all …]
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
11 #include <linux/cpu.h>
24 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
34 * non-SMP system gets one, then we don't know what to do. in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
59 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
62 static int riscv_intc_cpu_starting(unsigned int cpu) in riscv_intc_cpu_starting() argument
[all …]
/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-bcm6345-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * ENABLE/STATUS words are packed next to each other for each CPU:
19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
[all …]
Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
94 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
97 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
100 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
121 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
[all …]
Dirq-bcm2836.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/cpu.h>
14 #include <linux/irqchip/irq-bcm2836.h>
23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
27 int cpu) in bcm2836_arm_irqchip_mask_per_cpu_irq() argument
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
36 int cpu) in bcm2836_arm_irqchip_unmask_per_cpu_irq() argument
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq()
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq()
[all …]
Dirq-hip04.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon HiP04 INTC
5 * Copyright (C) 2002-2014 ARM Limited.
6 * Copyright (c) 2013-2014 HiSilicon Ltd.
7 * Copyright (c) 2013-2014 Linaro Ltd.
9 * Interrupt architecture for the HIP04 INTC:
14 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * associated CPU. The base address of the CPU interface is usually
18 * on the CPU it is accessed from.
20 * Note that IRQs 0-31 are special - they are local to each CPU.
[all …]
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
12 #include <linux/cpu.h>
29 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
36 * On RISC-V systems local interrupts are masked or unmasked by writing
44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
56 * are defined as (256 + n) and controlled by n-th bit in andes_intc_irq_mask()
[all …]
/kernel/linux/linux-6.6/arch/sh/include/mach-common/mach/
Dmicrodev.h1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/include/asm-sh/microdev.h
7 * Definitions for the SuperH SH4-202 MicroDev board.
17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
20 * correctly route - unfortunately, they have the same name and
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
26 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-bo…
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/
Dmicrodev.h1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/include/asm-sh/microdev.h
7 * Definitions for the SuperH SH4-202 MicroDev board.
17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
20 * correctly route - unfortunately, they have the same name and
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
26 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-bo…
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
42 cpu = <&CPU0>;
45 cpu = <&CPU1>;
[all …]
Darm-realview-eb.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/arm/
Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
42 cpu = <&CPU0>;
45 cpu = <&CPU1>;
[all …]
Darm-realview-eb.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
[all …]
Daxc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/arch/arc/boot/dts/
Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
[all …]
Daxc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/
Dcpu_irq.txt1 MIPS CPU interrupt controller
3 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
13 - compatible : Should be "mti,cpu-interrupt-controller"
16 cpu-irq: cpu-irq {
17 #address-cells = <0>;
19 interrupt-controller;
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
25 intc: intc@200 {
26 compatible = "ralink,rt2880-intc";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
13 source, should be 1 for intc
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
13 source, should be 1 for intc
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
16 device_type = "cpu";
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
16 device_type = "cpu";
[all …]

12345678910>>...26