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/kernel/linux/linux-5.10/include/crypto/
Dengine.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Crypto engine API
10 #include <linux/crypto.h>
14 #include <crypto/algapi.h>
15 #include <crypto/aead.h>
16 #include <crypto/akcipher.h>
17 #include <crypto/hash.h>
18 #include <crypto/skcipher.h>
22 * struct crypto_engine - crypto hardware engine
23 * @name: the engine name
[all …]
/kernel/linux/linux-6.6/drivers/crypto/aspeed/
DKconfig2 tristate "Support for Aspeed cryptographic engine driver"
6 Hash and Crypto Engine (HACE) is designed to accelerate the
13 bool "Enable Aspeed crypto debug messages"
16 Print Aspeed crypto debugging messages if you use this
22 bool "Enable Aspeed Hash & Crypto Engine (HACE) hash"
29 Select here to enable Aspeed Hash & Crypto Engine (HACE)
32 SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, and so on.
35 bool "Enable Aspeed Hash & Crypto Engine (HACE) crypto"
45 Select here to enable Aspeed Hash & Crypto Engine (HACE)
46 crypto driver.
[all …]
Daspeed-hace.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include "aspeed-hace.h"
7 #include <crypto/engine.h>
9 #include <linux/dma-mapping.h>
23 dev_info((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
26 dev_dbg((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
33 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine; in aspeed_hace_irq()
34 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine; in aspeed_hace_irq()
43 if (hash_engine->flags & CRYPTO_FLAGS_BUSY) in aspeed_hace_irq()
44 tasklet_schedule(&hash_engine->done_task); in aspeed_hace_irq()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/
Dqcom,inline-crypto-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
10 - Bjorn Andersson <andersson@kernel.org>
15 - enum:
16 - qcom,sm8450-inline-crypto-engine
17 - qcom,sm8550-inline-crypto-engine
18 - const: qcom,inline-crypto-engine
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Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
16 it is defined as a subnode of the NPE, if crypto support is
21 const: intel,ixp4xx-crypto
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Dmarvell-cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 "marvell,armada-370-crypto"
9 "marvell,armada-xp-crypto"
10 "marvell,armada-375-crypto"
11 "marvell,armada-38x-crypto"
12 - reg: base physical address of the engine and length of memory mapped
14 but this representation is deprecated and marvell,crypto-srams should
[all …]
Daspeed,ast2500-hace.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
10 - Neal Liu <neal_liu@aspeedtech.com>
13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
15 divided into two independently engines - Hash Engine and Crypto Engine.
20 - aspeed,ast2500-hace
21 - aspeed,ast2600-hace
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Dinside-secure-safexcel.txt1 Inside Secure SafeXcel cryptographic engine
4 - compatible: Should be "inside-secure,safexcel-eip197b",
5 "inside-secure,safexcel-eip197d" or
6 "inside-secure,safexcel-eip97ies".
7 - reg: Base physical address of the engine and length of memory mapped region.
8 - interrupts: Interrupt numbers for the rings and engine.
9 - interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
12 - clocks: Reference to the crypto engine clocks, the second clock is
14 - clock-names: mandatory if there is a second clock, in this case the
21 - "inside-secure,safexcel-eip197" is equivalent to
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/kernel/linux/linux-6.6/include/crypto/internal/
Dengine.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Crypto engine API
11 #include <crypto/algapi.h>
12 #include <crypto/engine.h>
22 * struct crypto_engine - crypto hardware engine
23 * @name: the engine name
24 * @idling: the engine is entering idle state
26 * @running: the engine is on working
27 * @retry_support: indication that the hardware allows re-execution
29 * crypto-engine, in head position to keep order
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/kernel/linux/linux-6.6/drivers/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Hardware crypto devices"
7 Say Y here to get to see options for hardware crypto devices and
14 source "drivers/crypto/allwinner/Kconfig"
20 Some VIA processors come with an integrated crypto engine
21 (so called VIA PadLock ACE, Advanced Cryptography Engine)
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
[all …]
/kernel/linux/linux-6.6/crypto/
Dcrypto_engine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Handle async block request by crypto hardware engine.
10 #include <crypto/internal/aead.h>
11 #include <crypto/internal/akcipher.h>
12 #include <crypto/internal/engine.h>
13 #include <crypto/internal/hash.h>
14 #include <crypto/internal/kpp.h>
15 #include <crypto/internal/skcipher.h>
35 * crypto_finalize_request - finalize one request if the request is done
36 * @engine: the hardware engine
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/kernel/linux/linux-6.6/include/crypto/
Dengine.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Crypto engine API
10 #include <crypto/aead.h>
11 #include <crypto/akcipher.h>
12 #include <crypto/hash.h>
13 #include <crypto/kpp.h>
14 #include <crypto/skcipher.h>
21 * struct crypto_engine_op - crypto hardware engine operations
25 int (*do_one_request)(struct crypto_engine *engine,
54 int crypto_transfer_aead_request_to_engine(struct crypto_engine *engine,
[all …]
/kernel/linux/linux-5.10/drivers/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Hardware crypto devices"
7 Say Y here to get to see options for hardware crypto devices and
14 source "drivers/crypto/allwinner/Kconfig"
20 Some VIA processors come with an integrated crypto engine
21 (so called VIA PadLock ACE, Advanced Cryptography Engine)
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
[all …]
/kernel/linux/linux-5.10/crypto/
Dcrypto_engine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Handle async block request by crypto hardware engine.
13 #include <crypto/engine.h>
20 * crypto_finalize_request - finalize one request if the request is done
21 * @engine: the hardware engine
25 static void crypto_finalize_request(struct crypto_engine *engine, in crypto_finalize_request() argument
38 if (!engine->retry_support) { in crypto_finalize_request()
39 spin_lock_irqsave(&engine->queue_lock, flags); in crypto_finalize_request()
40 if (engine->cur_req == req) { in crypto_finalize_request()
42 engine->cur_req = NULL; in crypto_finalize_request()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
[all …]
/kernel/linux/linux-5.10/drivers/crypto/allwinner/
DKconfig6 Say Y here to get to see options for Allwinner hardware crypto devices
19 Some Allwinner SoC have a crypto accelerator named
25 will be called sun4i-ss.
32 Select this option if you want to provide kernel-side support for
33 the Pseudo-Random Number Generator found in the Security System.
36 tristate "Support for Allwinner Crypto Engine cryptographic offloader"
46 Select y here to have support for the crypto Engine availlable on
48 The Crypto Engine handle AES/3DES ciphers in ECB/CBC mode.
51 will be called sun8i-ce.
54 bool "Enable sun8i-ce stats"
[all …]
/kernel/linux/linux-6.6/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <crypto/internal/hash.h>
6 #include <crypto/internal/skcipher.h>
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
[all …]
Dcesa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5 * driver supports the TDMA engine on platforms on which it is available.
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 #include <linux/dma-mapping.h>
32 /* Limit of the crypto queue before reaching the backlog */
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
43 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
44 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
[all …]
/kernel/linux/linux-6.6/drivers/crypto/allwinner/
DKconfig6 Say Y here to get to see options for Allwinner hardware crypto devices
19 Some Allwinner SoC have a crypto accelerator named
25 will be called sun4i-ss.
32 Select this option if you want to provide kernel-side support for
33 the Pseudo-Random Number Generator found in the Security System.
36 bool "Enable sun4i-ss stats"
40 Say y to enable sun4i-ss debug stats.
41 This will create /sys/kernel/debug/sun4i-ss/stats for displaying
45 tristate "Support for Allwinner Crypto Engine cryptographic offloader"
55 Select y here to have support for the crypto Engine available on
[all …]
/kernel/linux/linux-5.10/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <crypto/internal/hash.h>
6 #include <crypto/internal/skcipher.h>
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
[all …]
Dcesa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5 * driver supports the TDMA engine on platforms on which it is available.
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 #include <linux/dma-mapping.h>
32 /* Limit of the crypto queue before reaching the backlog */
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
43 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
44 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
[all …]
/kernel/linux/linux-5.10/Documentation/crypto/
Dcrypto_engine.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Crypto Engine
7 --------
8 The crypto engine (CE) API is a crypto queue manager.
11 -----------
18 struct crypto_engine engine;
22 The crypto engine only manages asynchronous requests in the form of
25 using container_of. In addition, the engine knows nothing about your
26 structure "``struct your_tfm_ctx``". The engine assumes (requires) the placement
30 -------------------
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/kernel/linux/linux-6.6/Documentation/crypto/
Dcrypto_engine.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Crypto Engine
7 --------
8 The crypto engine (CE) API is a crypto queue manager.
11 -----------
18 struct crypto_engine engine;
22 The crypto engine only manages asynchronous requests in the form of
25 using container_of. In addition, the engine knows nothing about your
26 structure "``struct your_tfm_ctx``". The engine assumes (requires) the placement
30 -------------------
[all …]
/kernel/linux/linux-6.6/drivers/soc/qcom/
Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
31 /* BIST ("built-in self-test") status flags */
38 #define qcom_ice_writel(engine, val, reg) \ argument
39 writel((val), (engine)->base + (reg))
41 #define qcom_ice_readl(engine, reg) \ argument
42 readl((engine)->base + (reg))
55 struct device *dev = ice->dev; in qcom_ice_check_supported()
67 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_check_supported()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dmarvell-cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 "marvell,armada-370-crypto"
9 "marvell,armada-xp-crypto"
10 "marvell,armada-375-crypto"
11 "marvell,armada-38x-crypto"
12 - reg: base physical address of the engine and length of memory mapped
14 but this representation is deprecated and marvell,crypto-srams should
[all …]

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