| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | gpmc-omap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
94 u32 t_ce; /* access time from CS asertion */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
105 u32 t_bacc; /* burst access valid clock to output delay */
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| /kernel/linux/linux-6.6/include/linux/platform_data/ |
| D | gpmc-omap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
94 u32 t_ce; /* access time from CS asertion */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
105 u32 t_bacc; /* burst access valid clock to output delay */
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | omap-gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
203 /* Structure to save gpmc cs context */
243 /* Define chip-selects as reserved by default until probe completes */
263 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
267 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
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| /kernel/linux/linux-6.6/drivers/memory/ |
| D | omap-gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
206 /* Structure to save gpmc cs context */
257 /* Define chip-selects as reserved by default until probe completes */
277 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
281 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
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| /kernel/linux/linux-5.10/include/linux/spi/ |
| D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later
25 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
31 * struct spi_statistics - statistics for spi transfers
34 * @messages: number of spi-messages handled
85 spin_lock_irqsave(&(stats)->lock, flags); \
86 (stats)->field += count; \
87 spin_unlock_irqrestore(&(stats)->lock, flags); \
94 * struct spi_delay - SPI delay information
95 * @value: Value for the delay
96 * @unit: Unit for the delay
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6dl-prtrvt.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "imx6qdl-prti6q.dtsi"
9 #include <dt-bindings/leds/common.h>
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_leds>;
25 led-debug0 {
28 linux,default-trigger = "heartbeat";
34 pinctrl-names = "default";
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| /kernel/linux/linux-6.6/include/linux/spi/ |
| D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later
33 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
39 * struct spi_statistics - statistics for spi transfers
40 * @syncp: seqcount to protect members in this struct for per-cpu update
41 * on 32-bit systems
43 * @messages: number of spi-messages handled
92 u64_stats_update_begin(&__lstats->syncp); \
93 u64_stats_add(&__lstats->field, count); \
94 u64_stats_update_end(&__lstats->syncp); \
103 u64_stats_update_begin(&__lstats->syncp); \
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| /kernel/linux/linux-5.10/net/ipv4/ |
| D | tcp_vegas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * IEEE Journal on Selected Areas in Communication, 13(8):1465--1480,
10 * ftp://ftp.cs.arizona.edu/xkernel/Papers/jsac.ps
12 * See http://www.cs.arizona.edu/xkernel/ for their implementation.
17 * using fine-grained timers, NewReno, and FACK.
19 * only every-other RTT during slow start, we increase during
29 * o When the sender re-starts from idle, it waits until it has
55 /* There are several situations when we must "re-start" Vegas:
65 * stale info -- both the saved cwnd and congestion feedback are
77 vegas->doing_vegas_now = 1; in vegas_enable()
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| /kernel/linux/linux-6.6/net/ipv4/ |
| D | tcp_vegas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * IEEE Journal on Selected Areas in Communication, 13(8):1465--1480,
10 * ftp://ftp.cs.arizona.edu/xkernel/Papers/jsac.ps
12 * See http://www.cs.arizona.edu/xkernel/ for their implementation.
17 * using fine-grained timers, NewReno, and FACK.
19 * only every-other RTT during slow start, we increase during
29 * o When the sender re-starts from idle, it waits until it has
55 /* There are several situations when we must "re-start" Vegas:
65 * stale info -- both the saved cwnd and congestion feedback are
77 vegas->doing_vegas_now = 1; in vegas_enable()
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| /kernel/linux/linux-5.10/sound/pci/emu10k1/ |
| D | emupcm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Multichannel PCM support Copyright (c) Lee Revell <rlrevell@joe-job.com>
9 * --
12 * --
16 #include <linux/delay.h>
28 if ((epcm = voice->epcm) == NULL) in snd_emu10k1_pcm_interrupt()
30 if (epcm->substream == NULL) in snd_emu10k1_pcm_interrupt()
33 dev_dbg(emu->card->dev, in snd_emu10k1_pcm_interrupt()
35 epcm->substream->runtime->hw->pointer(emu, epcm->substream), in snd_emu10k1_pcm_interrupt()
36 snd_pcm_lib_period_bytes(epcm->substream), in snd_emu10k1_pcm_interrupt()
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/delay.h>
23 #define DRIVER_NAME "spi-mt7621"
65 return spi_controller_get_devdata(spi->master); in spidev_to_mt7621_spi()
70 return ioread32(rs->base + reg); in mt7621_spi_read()
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| D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
148 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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| D | spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk/clk-conf.h>
10 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
35 #include <linux/spi/spi-mem.h>
51 spi_controller_put(spi->controller); in spidev_release()
52 kfree(spi->driver_override); in spidev_release()
53 free_percpu(spi->pcpu_statistics); in spidev_release()
63 len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1); in modalias_show()
64 if (len != -ENODEV) in modalias_show()
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
16 #include <linux/clk/clk-conf.h>
20 #include <linux/spi/spi-mem.h>
29 #include <linux/delay.h>
50 spi_controller_put(spi->controller); in spidev_release()
51 kfree(spi->driver_override); in spidev_release()
61 len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1); in modalias_show()
62 if (len != -ENODEV) in modalias_show()
65 return sprintf(buf, "%s%s\n", SPI_MODULE_PREFIX, spi->modalias); in modalias_show()
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| D | spi-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/delay.h>
21 #define DRIVER_NAME "spi-mt7621"
64 return spi_controller_get_devdata(spi->master); in spidev_to_mt7621_spi()
69 return ioread32(rs->base + reg); in mt7621_spi_read()
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| D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
123 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
128 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
133 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
138 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | pl35x-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/delay.h>
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
119 unsigned int cs; member
126 * struct pl35x_nandc - NAND flash controller driver structure
133 * @assigned_cs: List of assigned CS
162 if (section >= chip->ecc.steps) in pl35x_ecc_ooblayout16_ecc()
163 return -ERANGE; in pl35x_ecc_ooblayout16_ecc()
165 oobregion->offset = (section * chip->ecc.bytes); in pl35x_ecc_ooblayout16_ecc()
166 oobregion->length = chip->ecc.bytes; in pl35x_ecc_ooblayout16_ecc()
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_migrate.c | 1 // SPDX-License-Identifier: MIT
19 #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
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| D | intel_ring_submission.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
31 * set-context and then emitting the batch.
41 if (engine->class == RENDER_CLASS) { in set_hwstam()
42 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
56 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
59 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
67 return sg_page(obj->mm.pages->sgl); in status_page()
84 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_ring_submission.c | 2 * Copyright © 2008-2010 Intel Corporation
44 * set-context and then emitting the batch.
54 if (engine->class == RENDER_CLASS) { in set_hwstam()
55 if (INTEL_GEN(engine->i915) >= 6) in set_hwstam()
69 if (INTEL_GEN(engine->i915) >= 4) in set_hws_pga()
72 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
77 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
80 return sg_page(obj->mm.pages->sgl); in status_page()
97 if (IS_GEN(engine->i915, 7)) { in set_hwsp()
98 switch (engine->id) { in set_hwsp()
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| /kernel/linux/linux-6.6/include/linux/mtd/ |
| D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
176 * handle the tCCS delay which is required when a column change (RNDIN or
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
96 * ecc.correct() returns -EBADMSG.
122 * Chip requires ready check on read (for auto-incremented sequential read).
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
172 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173 * on the default ->cmdfunc() implementation, you may want to let the core
174 * handle the tCCS delay which is required when a column change (RNDIN or
[all …]
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