| /kernel/linux/linux-5.10/drivers/misc/habanalabs/common/ |
| D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
[all …]
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| /kernel/linux/linux-6.6/drivers/accel/habanalabs/common/ |
| D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
23 * enum hl_cs_wait_status - cs wait status
24 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
25 * @CS_WAIT_STATUS_COMPLETED: cs completed
26 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
47 * CS outcome store supports the following operations: in hl_push_cs_outcome()
48 * push outcome - store a recent CS outcome in the store in hl_push_cs_outcome()
49 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store in hl_push_cs_outcome()
51 * It has a pre-allocated amount of nodes, each node stores in hl_push_cs_outcome()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_migrate.c | 1 // SPDX-License-Identifier: MIT
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
80 vm->insert_page(vm, px_dma(pt), d->offset, in insert_pte()
[all …]
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| D | selftest_engine_cs.c | 1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(>->rps.num_waiters); in perf_begin()
30 queue_work(gt->i915->unordered_wq, >->rps.work); in perf_begin()
31 flush_work(>->rps.work); in perf_begin()
36 atomic_dec(>->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
44 struct drm_i915_private *i915 = engine->i915; in timestamp_reg()
47 return RING_TIMESTAMP_UDW(engine->mmio_base); in timestamp_reg()
49 return RING_TIMESTAMP(engine->mmio_base); in timestamp_reg()
[all …]
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| D | selftest_execlists.c | 1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
47 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
58 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
62 return -ETIME; in wait_for_submit()
78 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
84 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
88 if (rq->fence.error != -EIO) { in wait_for_reset()
90 engine->name, in wait_for_reset()
91 rq->fence.context, in wait_for_reset()
[all …]
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| D | selftest_timeline.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2018 Intel Corporation
29 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
32 return sg_page(obj->mm.pages->sgl); in hwsp_page()
39 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
49 err = i915_gem_object_lock(tl->hwsp_ggtt->obj, &ww); in selftest_tl_pin()
53 if (err == -EDEADLK) { in selftest_tl_pin()
81 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
83 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
96 while (count--) { in __mock_hwsp_timeline()
[all …]
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| D | selftest_ring_submission.c | 1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (GRAPHICS_VER(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
[all …]
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| D | selftest_rc6.c | 1 // SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = >->rc6; in live_rc6_manual()
47 if (!rc6->enabled) in live_rc6_manual()
51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
54 has_power = librapl_supported(gt->i915); in live_rc6_manual()
55 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
66 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
69 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
71 (res[1] - res[0]) >> 10); in live_rc6_manual()
72 err = -EINVAL; in live_rc6_manual()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/ |
| D | i915_perf.c | 2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
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| D | i915_request.c | 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
73 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); in igt_add_request()
75 return -ENOMEM; in igt_add_request()
87 int err = -EINVAL; in igt_wait_request()
91 request = mock_request(rcs0(i915)->kernel_context, T); in igt_wait_request()
93 return -ENOMEM; in igt_wait_request()
97 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
102 if (i915_request_wait(request, 0, T) != -ETIME) { in igt_wait_request()
114 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
124 if (i915_request_wait(request, 0, T / 2) != -ETIME) { in igt_wait_request()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/selftests/ |
| D | i915_perf.c | 2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strscpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
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| /kernel/linux/linux-5.10/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
[all …]
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| /kernel/linux/linux-6.6/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
[all …]
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-omap2-mcspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-omap2-mcspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
151 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
158 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
164 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | selftest_engine_cs.c | 2 * SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(>->rps.num_waiters); in perf_begin()
30 schedule_work(>->rps.work); in perf_begin()
31 flush_work(>->rps.work); in perf_begin()
36 atomic_dec(>->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 u32 *cs; in write_timestamp() local
47 cs = intel_ring_begin(rq, 4); in write_timestamp()
48 if (IS_ERR(cs)) in write_timestamp()
[all …]
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| D | selftest_lrc.c | 2 * SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
34 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
40 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); in create_scratch()
82 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
86 return -ETIME; in wait_for_submit()
102 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
108 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
114 if (rq->fence.error != -EIO) { in wait_for_reset()
116 engine->name, in wait_for_reset()
[all …]
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| D | selftest_ring_submission.c | 1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (INTEL_GEN(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
[all …]
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| D | selftest_rc6.c | 2 * SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = >->rc6; in live_rc6_manual()
46 if (!rc6->enabled) in live_rc6_manual()
50 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
53 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
64 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
67 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
69 (res[1] - res[0]) >> 10); in live_rc6_manual()
70 err = -EINVAL; in live_rc6_manual()
77 err = -EINVAL; in live_rc6_manual()
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/cachestat/ |
| D | test_cachestat.c | 1 // SPDX-License-Identifier: GPL-2.0
28 void print_cachestat(struct cachestat *cs) in print_cachestat() argument
32 cs->nr_cache, cs->nr_dirty, cs->nr_writeback, in print_cachestat()
33 cs->nr_evicted, cs->nr_recently_evicted); in print_cachestat()
46 goto out; in write_exactly()
68 remained -= read_len; in write_exactly()
84 remained -= write_len; in write_exactly()
93 out: in write_exactly()
126 struct cachestat cs; in test_cachestat() local
131 if (fd == -1) { in test_cachestat()
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/kpc2000/ |
| D | kpc2000_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2018 Daktronics
7 * Very loosely based on spi-omap2-mcspi.c
13 #include <linux/io-64-nonatomic-lo-hi.h>
126 unsigned int cs : 4; /* Chip Select */ member
163 kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx) in kp_spi_read_reg() argument
165 u64 __iomem *addr = cs->base; in kp_spi_read_reg()
168 if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0)) in kp_spi_read_reg()
169 return cs->conf_cache; in kp_spi_read_reg()
175 kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val) in kp_spi_write_reg() argument
[all …]
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| /kernel/linux/linux-6.6/kernel/cgroup/ |
| D | cpuset.c | 7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
24 #include "cgroup-internal.h"
53 * node binding, add this key to provide a quick low-cost judgment
99 * The user-configured masks can only be changed by writing to
113 * The user-configured masks are always the same with effective masks.
116 /* user-configured CPUs and Memory Nodes allow to tasks */
[all …]
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| /kernel/linux/linux-5.10/kernel/cgroup/ |
| D | cpuset.c | 7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
24 #include "cgroup-internal.h"
61 #include <linux/backing-dev.h>
91 * The user-configured masks can only be changed by writing to
105 * The user-configured masks are always the same with effective masks.
108 /* user-configured CPUs and Memory Nodes allow to tasks */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
168 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
169 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
170 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
171 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
180 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
204 u32 *cs; in restore_context_mmio_for_inhibit() local
207 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
208 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
162 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
163 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
174 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
198 u32 *cs; in restore_context_mmio_for_inhibit() local
201 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
202 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
[all …]
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