| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| D | fsl_esai.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25 * struct fsl_esai_soc_data - soc specific data
33 * struct fsl_esai - ESAI private data
38 * @coreclk: clock source to access register
39 * @extalclk: esai clock source to derive HCK, SCK and FS
40 * @fsysclk: system clock source to derive HCK, SCK and FS
41 * @spbaclk: SPBA clock (optional, depending on SoC design)
43 * @soc: soc specific data
51 * @hck_rate: clock rate of desired HCKx clock
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| D | fsl_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/dma/imx-dma.h>
26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
125 * Check if the divider is available for internal ratio mode
159 * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
162 * @pre_proc: return value for pre-processing option
163 * @post_proc: return value for post-processing option
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ |
| D | drm_scdc_helper.c | 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
33 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
34 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
35 * HDMI source and HDMI sink to exchange data. The same I2C interface that
42 * drm_scdc_read - read a block of data from SCDC
48 * Reads a block of data from SCDC, starting at a given offset.
75 return -EPROTO; in drm_scdc_read()
82 * drm_scdc_write - write a block of data to SCDC
85 * @buffer: block of data to write
88 * Writes a block of data to SCDC, starting at a given offset.
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| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_esai.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25 * struct fsl_esai_soc_data - soc specific data
35 * struct fsl_esai - ESAI private data
40 * @coreclk: clock source to access register
41 * @extalclk: esai clock source to derive HCK, SCK and FS
42 * @fsysclk: system clock source to derive HCK, SCK and FS
43 * @spbaclk: SPBA clock (optional, depending on SoC design)
45 * @soc: soc specific data
53 * @hck_rate: clock rate of desired HCKx clock
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| D | fsl_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-imx.h>
25 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
28 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
121 * Check if the divider is available for internal ratio mode
155 * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
158 * @pre_proc: return value for pre-processing option
159 * @post_proc: return value for post-processing option
188 /* Condition for selection of post-processing */ in fsl_asrc_sel_proc()
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| D | fsl_sai.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include "imx-pcm.h"
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
61 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
62 struct device *dev = &sai->pdev->dev; in fsl_sai_isr()
74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); in fsl_sai_isr()
104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); in fsl_sai_isr()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/display/ |
| D | drm_scdc_helper.c | 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
37 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
38 * HDMI source and HDMI sink to exchange data. The same I2C interface that
58 * drm_scdc_read - read a block of data from SCDC
64 * Reads a block of data from SCDC, starting at a given offset.
91 return -EPROTO; in drm_scdc_read()
98 * drm_scdc_write - write a block of data to SCDC
101 * @buffer: block of data to write
104 * Writes a block of data to SCDC, starting at a given offset.
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-cs2000-cp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * CS2000 -- CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
8 #include <linux/clk-provider.h>
24 #define Ratio_Val(x, nth) ((x >> (24 - (8 * nth))) & 0xFF)
25 #define Val_Ratio(x, nth) ((x & 0xFF) << (24 - (8 * nth)))
67 #define priv_to_client(priv) (priv->client)
68 #define priv_to_dev(priv) (&(priv_to_client(priv)->dev))
86 { .compatible = "cirrus,cs2000-cp", },
92 { "cs2000-cp", },
104 s32 data; in cs2000_bset() local
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| /kernel/linux/linux-5.10/drivers/media/platform/omap3isp/ |
| D | ispresizer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
42 * "TRM ES3.1, table 12-46"
52 * Constants for ratio calculation
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
75 /* For 8-phase 4-tap vertical filter: */
86 /* For 4-phase 7-tap horizontal filter: */
94 /* For 4-phase 7-tap vertical filter: */
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| /kernel/linux/linux-6.6/drivers/media/platform/ti/omap3isp/ |
| D | ispresizer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
42 * "TRM ES3.1, table 12-46"
52 * Constants for ratio calculation
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
75 /* For 8-phase 4-tap vertical filter: */
86 /* For 4-phase 7-tap horizontal filter: */
94 /* For 4-phase 7-tap vertical filter: */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/ |
| D | samsung,exynos-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | cs4270.c | 6 * Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed
15 * - Software mode is supported. Stand-alone mode is not supported.
16 * - Only I2C is supported, not SPI
17 * - Support for master and slave mode
18 * - The machine driver's 'startup' function must call
20 * - Only I2S and left-justified modes are supported
21 * - Power management is supported
36 * The codec isn't really big-endian or little-endian, since the I2S
37 * interface requires data to be sent serially with the MSbit first.
60 #define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1)
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| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | cs4270.c | 6 * Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed
15 * - Software mode is supported. Stand-alone mode is not supported.
16 * - Only I2C is supported, not SPI
17 * - Support for master and slave mode
18 * - The machine driver's 'startup' function must call
20 * - Only I2S and left-justified modes are supported
21 * - Power management is supported
51 #define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1)
101 /* Power-on default values for the registers
103 * This array contains the power-on default values of the registers, with the
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| /kernel/linux/linux-5.10/Documentation/driver-api/thermal/ |
| D | intel_powerclamp.rst | 6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
30 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
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| /kernel/linux/linux-6.6/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
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| /kernel/linux/linux-6.6/Documentation/admin-guide/thermal/ |
| D | intel_powerclamp.rst | 6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
[all …]
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | socfpga-a10.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/fpga-mgr.h>
54 /* FPGA CD Ratio Value */
65 * struct a10_fpga_priv - private data for fpga manager
67 * @fpga_data_addr: iomap for single address data register to FPGA
68 * @clk: clock
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
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| /kernel/linux/linux-5.10/drivers/iio/adc/ |
| D | sc27xx_adc.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/nvmem-consumer.h>
57 /* Timeout (us) for ADC data conversion according to ADC datasheet */
64 /* ADC voltage ratio definition */
93 * should use the small-scale graph, and if more than 1.2v, we should use the
94 * big-scale graph.
118 return ((calib_data & 0xff) + calib_adc - 128) * 4; in sc27xx_adc_get_calib_data()
121 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, in sc27xx_adc_scale_calibration() argument
142 cell = nvmem_cell_get(data->dev, cell_name); in sc27xx_adc_scale_calibration()
155 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); in sc27xx_adc_scale_calibration()
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| /kernel/linux/linux-5.10/drivers/char/hw_random/ |
| D | cctrng.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
23 #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
32 /* data circular buffer in words must be:
33 * - of a power-of-2 size (limitation of circ_buf.h macros)
34 * - at least 6, the size generated in the EHR according to HW implementation
41 * - SAMPLE_CNT is input value from the characterisation process
42 * - all the rest are constants
59 * Value of 0 indicates non-valid rosc
68 /* pending_hw - 1 when HW is pending, 0 when it is idle */
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | opp2xxx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
13 * these combinations is via the 'ratio's' which the clocks operate with
14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
16 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
19 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | opp2xxx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
13 * these combinations is via the 'ratio's' which the clocks operate with
14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
16 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
19 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
[all …]
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| /kernel/linux/linux-6.6/drivers/char/hw_random/ |
| D | cctrng.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
23 #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
32 /* data circular buffer in words must be:
33 * - of a power-of-2 size (limitation of circ_buf.h macros)
34 * - at least 6, the size generated in the EHR according to HW implementation
41 * - SAMPLE_CNT is input value from the characterisation process
42 * - all the rest are constants
59 * Value of 0 indicates non-valid rosc
68 /* pending_hw - 1 when HW is pending, 0 when it is idle */
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| /kernel/linux/linux-6.6/drivers/media/platform/samsung/s3c-camif/ |
| D | camif-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include <media/media-device.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/videobuf2-v4l2.h>
31 #include <media/videobuf2-dma-contig.h>
33 #include "camif-core.h"
36 /* HCLK CAMIF clock */
38 /* CAMIF / external camera sensor master clock */
94 * s3c_camif_find_format() - lookup camif color format by fourcc or an index
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| /kernel/linux/linux-5.10/drivers/media/platform/s3c-camif/ |
| D | camif-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #include <media/media-device.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/videobuf2-v4l2.h>
32 #include <media/videobuf2-dma-contig.h>
34 #include "camif-core.h"
37 /* HCLK CAMIF clock */
39 /* CAMIF / external camera sensor master clock */
95 * s3c_camif_find_format() - lookup camif color format by fourcc or an index
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