| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | axp20x.txt | 4 axp152 (X-Powers)
5 axp202 (X-Powers)
6 axp209 (X-Powers)
7 axp221 (X-Powers)
8 axp223 (X-Powers)
9 axp803 (X-Powers)
10 axp806 (X-Powers)
11 axp809 (X-Powers)
12 axp813 (X-Powers)
20 - compatible: should be one of:
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5758.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
19 spi-cpha: true
21 adi,dc-dc-mode:
25 Mode of operation of the dc-to-dc converter
27 In this mode, the AD5758 circuitry senses the output voltage and
32 In this mode, the VDPC+ voltage is user-programmable to a fixed level
36 voltage output at the VIOUT pin. Only one mode can be enabled at
[all …]
|
| D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/dac/ |
| D | ad5755.txt | 1 * Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
4 - compatible: Has to contain one of the following:
6 adi,ad5755-1
11 - reg: spi chip select number for the device
12 - spi-cpha or spi-cpol: is the only modes that is supported
15 - spi-max-frequency: Definition as per
16 Documentation/devicetree/bindings/spi/spi-bus.txt
19 See include/dt-bindings/iio/ad5755.h
20 - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
23 - adi,dc-dc-phase:
[all …]
|
| D | ad5758.txt | 4 - compatible: Must be "adi,ad5758"
5 - reg: SPI chip select number for the device
6 - spi-max-frequency: Max SPI frequency to use (< 50000000)
7 - spi-cpha: is the only mode that is supported
11 - adi,dc-dc-mode: Mode of operation of the dc-to-dc converter
13 In this mode, the AD5758 circuitry senses the output
19 In this mode, the VDPC+ voltage is user-programmable to
24 current or voltage output at the VIOUT pin. Only one mode
28 * 1: DPC current mode
29 * 2: DPC voltage mode
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/atmel-hlcdc/ |
| D | atmel_hlcdc_dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
14 #include <linux/mfd/atmel-hlcdc.h>
100 .name = "high-end-overlay",
212 .name = "high-end-overlay",
330 .name = "high-end-overlay",
425 .name = "high-end-overlay",
467 .compatible = "atmel,at91sam9n12-hlcdc",
471 .compatible = "atmel,at91sam9x5-hlcdc",
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "dc.h"
36 stats->frames = 0; in tegra_dc_stats_reset()
37 stats->vblank = 0; in tegra_dc_stats_reset()
38 stats->underflow = 0; in tegra_dc_stats_reset()
39 stats->overflow = 0; in tegra_dc_stats_reset()
43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
48 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/atmel-hlcdc/ |
| D | atmel_hlcdc_dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
14 #include <linux/mfd/atmel-hlcdc.h>
100 .name = "high-end-overlay",
212 .name = "high-end-overlay",
330 .name = "high-end-overlay",
425 .name = "high-end-overlay",
467 .compatible = "atmel,at91sam9n12-hlcdc",
471 .compatible = "atmel,at91sam9x5-hlcdc",
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/tegra/ |
| D | dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
32 #include "dc.h"
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_enc_cfg.c | 29 #define DC_LOGGER dc->ctx->logger
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
46 if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) { in is_dig_link_enc_stream()
47 if (dc_is_dp_signal(stream->signal)) { in is_dig_link_enc_stream()
51 stream->ctx->dc->link_srv->dp_decide_link_settings(stream, &link_settings); in is_dig_link_enc_stream()
67 static struct link_enc_assignment get_assignment(struct dc *dc, int i) in get_assignment() argument
71 if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT) in get_assignment()
72 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i]; in get_assignment()
74 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; in get_assignment()
[all …]
|
| D | dc.c | 27 #include "dc.h"
81 dc->ctx
84 dc->ctx->logger
86 static const char DC_BUILD_ID[] = "production-build";
91 * DC is the OS-agnostic component of the amdgpu DC driver.
93 * DC maintains and validates a set of structs representing the state of the
96 * Main DC HW structs:
98 * struct dc - The central struct. One per driver. Created on driver load,
101 * struct dc_context - One per driver.
102 * Used as a backpointer by most other structs in dc.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/gpu/amdgpu/display/ |
| D | display-manager.rst | 8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 2 * Copyright 2012-14 Advanced Micro Devices, Inc.
62 * or has to be fetched by hardware (DMA mode)
71 /* If hardware mode is used, the base address where DMDATA surface is located */
94 /* source MPCC instance. for use by internally by dc */
199 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
216 /* Output from DC when stream state is committed or altered
217 * DC may only access these values during:
285 void dc_commit_updates_for_stream(struct dc *dc,
294 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
296 uint8_t dc_get_current_stream_count(struct dc *dc);
[all …]
|
| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | ad5755.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
70 * struct ad5755_platform_data - AD5755 DAC driver platform data
71 * @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
73 * @dc_dc_phase: DC-DC converter phase.
74 * @dc_dc_freq: DC-DC converter frequency.
75 * @dc_dc_maxv: DC-DC maximum allowed boost voltage.
76 * @dac.mode: The mode to be used for the DAC output.
91 enum ad5755_mode mode; member
|
| /kernel/linux/linux-5.10/drivers/usb/musb/ |
| D | musb_cppi41.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/dma-mapping.h>
13 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
50 unsigned int mode);
59 if (cppi41_channel->is_tx) in save_rx_toggle()
61 if (!is_host_active(cppi41_channel->controller->controller.musb)) in save_rx_toggle()
64 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle()
67 cppi41_channel->usb_toggle = toggle; in save_rx_toggle()
72 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep; in update_rx_toggle()
73 struct musb *musb = hw_ep->musb; in update_rx_toggle()
[all …]
|
| /kernel/linux/linux-6.6/drivers/usb/musb/ |
| D | musb_cppi41.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/dma-mapping.h>
13 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
50 unsigned int mode);
59 if (cppi41_channel->is_tx) in save_rx_toggle()
61 if (!is_host_active(cppi41_channel->controller->controller.musb)) in save_rx_toggle()
64 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle()
67 cppi41_channel->usb_toggle = toggle; in save_rx_toggle()
72 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep; in update_rx_toggle()
73 struct musb *musb = hw_ep->musb; in update_rx_toggle()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 58 hws->ctx
60 hws->regs->reg
62 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
72 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
76 if (plane_state->blend_tf) { in dcn30_set_blend_lut()
77 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) in dcn30_set_blend_lut()
78 blend_lut = &plane_state->blend_tf->pwl; in dcn30_set_blend_lut()
79 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { in dcn30_set_blend_lut()
81 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 2 * Copyright 2012-14 Advanced Micro Devices, Inc.
62 * or has to be fetched by hardware (DMA mode)
71 /* If hardware mode is used, the base address where DMDATA surface is located */
93 /* source MPCC instance. for use by internally by dc */
266 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
281 /* Output from DC when stream state is committed or altered
282 * DC may only access these values during:
367 bool dc_update_planes_and_stream(struct dc *dc,
382 void dc_commit_updates_for_stream(struct dc *dc,
391 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
[all …]
|
| D | dc.h | 2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
99 // for example, 1080p -> 8K is 4.0, or 4000 raw value
107 // for example, 8K -> 1080p is 0.25, or 250 raw value
119 * DOC: color-management-caps
124 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
131 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
147 * struct dpp_color_caps - color pipeline capabilities for display pipe and
152 * just plain 256-entry lookup
161 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
162 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 43 hws->ctx
45 hws->regs->reg
49 hws->shifts->field_name, hws->masks->field_name
63 …config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_… in mmhub_update_page_table_config()
67 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn21_init_sys_ctx() argument
71 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; in dcn21_init_sys_ctx()
72 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; in dcn21_init_sys_ctx()
73 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; in dcn21_init_sys_ctx()
74 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; in dcn21_init_sys_ctx()
75 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; in dcn21_init_sys_ctx()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 43 hws->ctx
45 hws->regs->reg
49 hws->shifts->field_name, hws->masks->field_name
63 …config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_… in mmhub_update_page_table_config()
67 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn21_init_sys_ctx() argument
71 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; in dcn21_init_sys_ctx()
72 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; in dcn21_init_sys_ctx()
73 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; in dcn21_init_sys_ctx()
74 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; in dcn21_init_sys_ctx()
75 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; in dcn21_init_sys_ctx()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 28 #include "dc.h"
725 .dwb_fi_phase = -1, // -1 = disable,
758 return &dpp->base; in dcn30_dpp_create()
778 return &opp->base; in dcn30_opp_create()
796 ctx->dc->caps.extended_aux_timeout_support); in dcn30_aux_engine_create()
798 return &aux_engine->base; in dcn30_aux_engine_create()
854 return &mpc30->base; in dcn30_mpc_create()
874 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn30_hubbub_create()
876 vmid->ctx = ctx; in dcn30_hubbub_create()
878 vmid->regs = &vmid_regs[i]; in dcn30_hubbub_create()
[all …]
|
| D | dcn30_hwseq.c | 61 hws->ctx
63 hws->regs->reg
65 dc->ctx->logger
70 hws->shifts->field_name, hws->masks->field_name
75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
79 if (plane_state->blend_tf) { in dcn30_set_blend_lut()
80 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) in dcn30_set_blend_lut()
81 blend_lut = &plane_state->blend_tf->pwl; in dcn30_set_blend_lut()
82 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { in dcn30_set_blend_lut()
84 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
[all …]
|
| /kernel/linux/linux-6.6/drivers/md/bcache/ |
| D | request.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Main bcache entry point - handle a read or a write request and decide what to
19 #include <linux/backing-dev.h>
30 static unsigned int cache_mode(struct cached_dev *dc) in cache_mode() argument
32 return BDEV_CACHE_MODE(&dc->sb); in cache_mode()
35 static bool verify(struct cached_dev *dc) in verify() argument
37 return dc->verify; in verify()
53 k->ptr[KEY_PTRS(k)] = csum & (~0ULL >> 1); in bio_csum()
62 struct bkey *replace_key = op->replace ? &op->replace_key : NULL; in bch_data_insert_keys()
65 if (!op->replace) in bch_data_insert_keys()
[all …]
|
| /kernel/linux/linux-5.10/drivers/md/bcache/ |
| D | request.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Main bcache entry point - handle a read or a write request and decide what to
19 #include <linux/backing-dev.h>
30 static unsigned int cache_mode(struct cached_dev *dc) in cache_mode() argument
32 return BDEV_CACHE_MODE(&dc->sb); in cache_mode()
35 static bool verify(struct cached_dev *dc) in verify() argument
37 return dc->verify; in verify()
53 k->ptr[KEY_PTRS(k)] = csum & (~0ULL >> 1); in bio_csum()
62 struct bkey *replace_key = op->replace ? &op->replace_key : NULL; in bch_data_insert_keys()
65 if (!op->replace) in bch_data_insert_keys()
[all …]
|