| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 30 #include "dc.h"
135 #define SRI(reg_name, block, id)\ argument
136 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 mm ## block ## id ## _ ## reg_name
139 #define SRI2_DWB(reg_name, block, id)\ argument
145 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
148 #define SRIR(var_name, reg_name, block, id)\ argument
149 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 mm ## block ## id ## _ ## reg_name
152 #define SRII(reg_name, block, id)\ argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 dc->ctx->logger
118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
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| D | dce110_hw_sequencer.c | 27 #include "dc.h"
73 * For eDP, after power-up/power/down,
83 hws->ctx
88 hws->regs->reg
92 hws->shifts->field_name, hws->masks->field_name
100 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
103 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
106 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
109 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
113 #define HW_REG_BLND(reg, id)\ argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 27 #include "dc.h"
112 #define SRI(reg_name, block, id)\ argument
113 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
114 mm ## block ## id ## _ ## reg_name
117 #define SRII(reg_name, block, id)\ argument
118 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 mm ## block ## id ## _ ## reg_name
121 #define VUPDATE_SRII(reg_name, block, id)\ argument
122 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
123 mm ## reg_name ## 0 ## _ ## block ## id
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.c | 1 // SPDX-License-Identifier: MIT
28 #include "dc.h"
108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
115 #define SR_ARR(reg_name, id) \ argument
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
119 REG_STRUCT[id].reg_name = value
121 #define SRI(reg_name, block, id)\ argument
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
59 dc->ctx->logger
120 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
121 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
124 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
125 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
133 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
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| D | dce110_hw_sequencer.c | 29 #include "dc.h"
69 * For eDP, after power-up/power/down,
79 hws->ctx
84 hws->regs->reg
88 hws->shifts->field_name, hws->masks->field_name
96 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
99 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
102 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
105 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
109 #define HW_REG_BLND(reg, id)\ argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 29 #include "dc.h"
87 .LineBufferFixedBpp = -1,
176 #define SRI(reg_name, block, id)\ argument
177 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 mm ## block ## id ## _ ## reg_name
181 #define SRII(reg_name, block, id)\ argument
182 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 mm ## block ## id ## _ ## reg_name
185 #define VUPDATE_SRII(reg_name, block, id)\ argument
186 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 30 #include "dc.h"
495 #define SRI(reg_name, block, id)\ argument
496 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
497 mm ## block ## id ## _ ## reg_name
499 #define SRIR(var_name, reg_name, block, id)\ argument
500 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
503 #define SRII(reg_name, block, id)\ argument
504 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | fsl,imx8qxp-pixel-link.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
36 fsl,dc-stream-id:
39 u8 value representing the display controller stream index that the pixel
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
31 #include "dc.h"
83 if (link->hpd_gpio) { in dc_link_destruct()
84 dal_gpio_destroy_irq(&link->hpd_gpio); in dc_link_destruct()
85 link->hpd_gpio = NULL; in dc_link_destruct()
88 if (link->ddc) in dc_link_destruct()
89 dal_ddc_service_destroy(&link->ddc); in dc_link_destruct()
91 if (link->panel_cntl) in dc_link_destruct()
92 link->panel_cntl->funcs->destroy(&link->panel_cntl); in dc_link_destruct()
94 if (link->link_enc) in dc_link_destruct()
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| D | dc_link_hwss.c | 5 #include "dc.h"
46 return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset); in is_immediate_downstream()
55 if (!link->aux_access_disabled && in core_link_read_dpcd()
56 !dm_helpers_dp_read_dpcd(link->ctx, in core_link_read_dpcd()
70 if (!link->aux_access_disabled && in core_link_write_dpcd()
71 !dm_helpers_dp_write_dpcd(link->ctx, in core_link_write_dpcd()
85 if (link->sync_lt_in_progress) in dp_receiver_power_ctrl()
98 struct link_encoder *link_enc = link->link_enc; in dp_enable_link_phy()
99 struct dc *dc = link->ctx->dc; in dp_enable_link_phy() local
100 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_enable_link_phy()
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| D | dc_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
142 struct resource_pool *dc_create_resource_pool(struct dc *dc, in dc_create_resource_pool() argument
152 init_data->num_virtual_links, dc); in dc_create_resource_pool()
156 init_data->num_virtual_links, dc); in dc_create_resource_pool()
160 init_data->num_virtual_links, dc); in dc_create_resource_pool()
165 init_data->num_virtual_links, dc); in dc_create_resource_pool()
169 init_data->num_virtual_links, dc); in dc_create_resource_pool()
173 init_data->num_virtual_links, dc); in dc_create_resource_pool()
177 init_data->num_virtual_links, dc); in dc_create_resource_pool()
181 init_data->num_virtual_links, dc, in dc_create_resource_pool()
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| D | dc.c | 30 #include "dc.h"
74 dc->ctx
77 dc->ctx->logger
79 static const char DC_BUILD_ID[] = "production-build";
84 * DC is the OS-agnostic component of the amdgpu DC driver.
86 * DC maintains and validates a set of structs representing the state of the
89 * Main DC HW structs:
91 * struct dc - The central struct. One per driver. Created on driver load,
94 * struct dc_context - One per driver.
95 * Used as a backpointer by most other structs in dc.
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 #define SRI(reg_name, block, id)\ argument
40 .reg_name = mm ## block ## id ## _ ## reg_name
55 /*ClocksStateInvalid - should not be used*/
57 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
67 const struct dc *dc, in determine_sclk_from_bounding_box() argument
76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
80 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) in determine_sclk_from_bounding_box()
81 return dc->sclk_lvls.clocks_in_khz[i]; in determine_sclk_from_bounding_box()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 28 #include "dc.h"
249 #define SRI(reg_name, block, id)\ argument
250 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
251 mm ## block ## id ## _ ## reg_name
253 #define SRI2(reg_name, block, id)\ argument
257 #define SRIR(var_name, reg_name, block, id)\ argument
258 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
259 mm ## block ## id ## _ ## reg_name
261 #define SRII(reg_name, block, id)\ argument
262 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 #define SRI(reg_name, block, id)\ argument
40 .reg_name = mm ## block ## id ## _ ## reg_name
55 /*ClocksStateInvalid - should not be used*/
57 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
67 const struct dc *dc, in determine_sclk_from_bounding_box() argument
76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
80 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) in determine_sclk_from_bounding_box()
81 return dc->sclk_lvls.clocks_in_khz[i]; in determine_sclk_from_bounding_box()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| D | link_fpga.c | 36 struct dc *dc = pipe_ctx->stream->ctx->dc; in dp_fpga_hpo_enable_link_and_stream() local
37 struct dc_stream_state *stream = pipe_ctx->stream; in dp_fpga_hpo_enable_link_and_stream() local
41 uint8_t vc_id = 1; /// VC ID always 1 for SST in dp_fpga_hpo_enable_link_and_stream()
42 struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings; in dp_fpga_hpo_enable_link_and_stream()
43 const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res); in dp_fpga_hpo_enable_link_and_stream()
44 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); in dp_fpga_hpo_enable_link_and_stream()
46 stream->link->cur_link_settings = link_settings; in dp_fpga_hpo_enable_link_and_stream()
48 if (link_hwss->ext.enable_dp_link_output) in dp_fpga_hpo_enable_link_and_stream()
49 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res, in dp_fpga_hpo_enable_link_and_stream()
50 stream->signal, pipe_ctx->clock_source->id, in dp_fpga_hpo_enable_link_and_stream()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_dpms.c | 27 * This file owns the programming sequence of stream's dpms state associated
28 * with the link and link's enable/disable sequences as result of the stream's
31 * TODO - The reason link owns stream's dpms programming sequence is
34 * stream state programming sequence. This creates a gray area where the
35 * boundary between link and stream is not clearly defined.
68 #include "dc/dcn30/dcn30_vpg.h"
74 void link_blank_all_dp_displays(struct dc *dc) in link_blank_all_dp_displays() argument
80 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
81 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
82 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 29 #include "dc.h"
81 struct dc *dc,
85 struct dc *dc, struct dc_state *context,
90 struct dc *dc, struct dc_state *context);
93 * @populate_dml_pipes - Populate pipe data struct
99 struct dc *dc,
111 struct dc *dc,
116 * Unassign a link encoder from a stream.
123 struct dc_stream_state *stream);
126 struct dc *dc,
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_enc_cfg.c | 29 #define DC_LOGGER dc->ctx->logger
31 /* Check whether stream is supported by DIG link encoders. */
32 static bool is_dig_link_enc_stream(struct dc_stream_state *stream) in is_dig_link_enc_stream() argument
39 if (stream) { in is_dig_link_enc_stream()
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
43 /* Need to check link signal type rather than stream signal type which may not in is_dig_link_enc_stream()
46 if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) { in is_dig_link_enc_stream()
47 if (dc_is_dp_signal(stream->signal)) { in is_dig_link_enc_stream()
51 stream->ctx->dc->link_srv->dp_decide_link_settings(stream, &link_settings); in is_dig_link_enc_stream()
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| D | dc_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
86 #define UNABLE_TO_SPLIT -1
196 struct resource_pool *dc_create_resource_pool(struct dc *dc, in dc_create_resource_pool() argument
206 init_data->num_virtual_links, dc); in dc_create_resource_pool()
210 init_data->num_virtual_links, dc); in dc_create_resource_pool()
214 init_data->num_virtual_links, dc); in dc_create_resource_pool()
219 init_data->num_virtual_links, dc); in dc_create_resource_pool()
223 init_data->num_virtual_links, dc); in dc_create_resource_pool()
227 init_data->num_virtual_links, dc); in dc_create_resource_pool()
231 init_data->num_virtual_links, dc); in dc_create_resource_pool()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| D | link_hwss_dio.c | 32 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
34 stream_encoder->funcs->set_throttled_vcp_size( in set_dio_throttled_vcp_size()
41 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); in setup_dio_stream_encoder()
42 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
44 link_enc->funcs->connect_dig_be_to_fe(link_enc, in setup_dio_stream_encoder()
45 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
46 if (dc_is_dp_signal(pipe_ctx->stream->signal)) in setup_dio_stream_encoder()
47 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link, in setup_dio_stream_encoder()
49 if (stream_enc->funcs->map_stream_to_link) in setup_dio_stream_encoder()
50 stream_enc->funcs->map_stream_to_link(stream_enc, in setup_dio_stream_encoder()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
63 dc->ctx->logger
119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_edp_panel_control.c | 38 #include "dc/dc_dmub_srv.h"
90 link->panel_mode = panel_mode; in dp_set_panel_mode()
93 link->link_index, in dp_set_panel_mode()
94 link->dpcd_caps.panel_mode_edp, in dp_set_panel_mode()
104 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { in dp_get_panel_mode()
106 switch (link->dpcd_caps.branch_dev_id) { in dp_get_panel_mode()
110 * provide sink device id, alternate scrambler in dp_get_panel_mode()
115 link->dpcd_caps.branch_dev_name, in dp_get_panel_mode()
118 link->dpcd_caps. in dp_get_panel_mode()
126 * sink device id, alternate scrambler scheme will in dp_get_panel_mode()
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