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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dbrcm,brcmstb-memc-ddr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
[all …]
Dqca,ath79-ddr-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr-wb-channel-cells"
[all …]
Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/freescale/imx8mp/sys/
Dmetrics.json3 "BriefDescription": "bytes of all masters read from ddr",
11 "BriefDescription": "bytes of all masters write to ddr",
19 "BriefDescription": "bytes of a53 core read from ddr",
27 "BriefDescription": "bytes of a53 core write to ddr",
35 "BriefDescription": "bytes of supermix(m7) core read from ddr",
43 "BriefDescription": "bytes of supermix(m7) write to ddr",
51 "BriefDescription": "bytes of gpu 3d read from ddr",
59 "BriefDescription": "bytes of gpu 3d write to ddr",
67 "BriefDescription": "bytes of gpu 2d read from ddr",
75 "BriefDescription": "bytes of gpu 2d write to ddr",
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr-pmu
[all …]
Damlogic,g12-ddr-pmu.yaml4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
49 compatible = "amlogic,g12a-ddr-pmu";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dath79-ddr-controller.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
15 - #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
21 compatible = "qca,ar9132-ddr-controller",
22 "qca,ar7240-ddr-controller";
[all …]
Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller binding
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mp-ddr-pmu
21 - fsl,imx8mm-ddr-pmu
22 - fsl,imx8mn-ddr-pmu
23 - fsl,imx8mq-ddr-pmu
24 - fsl,imx8mp-ddr-pmu
25 - const: fsl,imx8m-ddr-pmu
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dbrcmstb_memc.c3 * DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
181 .compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
185 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
189 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
193 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
197 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
201 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
205 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
209 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
213 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-rc32434/
Dddr.h2 * Definitions for the DDR registers
34 /* DDR register structure */
51 /* DDR banks masks */
56 /* DDR bank0 registers */
86 /* DDR bank C registers */
91 /* Custom DDR bank registers */
102 /* DDR QSC registers */
114 /* DDR LLC registers */
126 /* DDR LLFC registers */
132 /* DDR DLLTA registers */
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-rc32434/
Dddr.h2 * Definitions for the DDR registers
34 /* DDR register structure */
51 /* DDR banks masks */
56 /* DDR bank0 registers */
86 /* DDR bank C registers */
91 /* Custom DDR bank registers */
102 /* DDR QSC registers */
114 /* DDR LLC registers */
126 /* DDR LLFC registers */
132 /* DDR DLLTA registers */
[all …]
/kernel/linux/linux-5.10/include/linux/
Dfsl-diu-fb.h65 * These are the fields of area descriptor(in DDR memory) for every plane
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
92 /* Word 3(32-bit) in DDR memory */
100 /* Word 4(32-bit) in DDR memory */
108 /* Word 5(32-bit) in DDR memory */
116 /* Word 6(32-bit) in DDR memory */
122 /* Word 7(32-bit) in DDR memory */
129 /* Word 8(32-bit) in DDR memory */
[all …]
/kernel/linux/linux-6.6/include/linux/
Dfsl-diu-fb.h65 * These are the fields of area descriptor(in DDR memory) for every plane
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
92 /* Word 3(32-bit) in DDR memory */
100 /* Word 4(32-bit) in DDR memory */
108 /* Word 5(32-bit) in DDR memory */
116 /* Word 6(32-bit) in DDR memory */
122 /* Word 7(32-bit) in DDR memory */
129 /* Word 8(32-bit) in DDR memory */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/thermal/
Dintel_dptf.rst188 DDR (Double Data Rate) and DLVR (Digital Linear Voltage Regulator)
209 DRAM devices of DDR IO interface and their power plane can generate EMI
211 mechanism by which DDR data rates can be changed if several conditions
212 are met: there is strong RFI interference because of DDR; CPU power
213 management has no other restriction in changing DDR data rates;
214 PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
215 DDR-RFIM) for Wi-Fi from BIOS.
249 Request the restriction of specific DDR data rate and set this
257 Restricted DDR data rate for RFI protection: Lower Limit
260 Restricted DDR data rate for RFI protection: Upper Limit
[all …]
/kernel/linux/linux-6.6/arch/mips/rb532/
Dprom.c21 #include <asm/mach-rc32434/ddr.h>
29 .name = "ddr-reg",
103 struct ddr_ram __iomem *ddr; in prom_init() local
107 ddr = ioremap(ddr_reg[0].start, in prom_init()
110 if (!ddr) { in prom_init()
111 printk(KERN_ERR "Unable to remap DDR register\n"); in prom_init()
115 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
116 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()
/kernel/linux/linux-5.10/arch/mips/rb532/
Dprom.c22 #include <asm/mach-rc32434/ddr.h>
30 .name = "ddr-reg",
109 struct ddr_ram __iomem *ddr; in prom_init() local
113 ddr = ioremap(ddr_reg[0].start, in prom_init()
116 if (!ddr) { in prom_init()
117 printk(KERN_ERR "Unable to remap DDR register\n"); in prom_init()
121 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
122 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()

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