| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | gpmc-nor.txt | 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
[all …]
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| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
[all …]
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-dw-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
17 #include <linux/spi/spi-mem.h>
21 #include "spi-dw.h"
64 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
65 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
67 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
68 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
69 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
70 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-dw-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
16 #include <linux/spi/spi-mem.h>
20 #include "spi-dw.h"
63 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
64 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
65 if (!dws->debugfs) in dw_spi_debugfs_init()
66 return -ENOMEM; in dw_spi_debugfs_init()
68 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
69 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.txt | 4 external memory (such as NAND or other memory-mapped peripherals) whereas
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
31 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
51 - compatible: should be one of:
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.txt | 4 external memory (such as NAND or other memory-mapped peripherals) whereas
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
31 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
51 - compatible: should be one of:
[all …]
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| /kernel/linux/linux-6.6/Documentation/translations/sp_SP/process/ |
| D | kernel-enforcement-statement.rst | 1 .. include:: ../disclaimer-sp.rst
3 :Original: :ref:`Documentation/process/kernel-enforcement-statement.rst <process_statement_kernel>`
8 Aplicación de la licencia en el kernel Linux
12 se utiliza nuestro software y cómo se aplica la licencia de nuestro software.
13 El cumplimiento de las obligaciones de intercambio recíproco de GPL-2.0 son
14 fundamentales en el largo plazo para la sostenibilidad de nuestro software
17 Aunque existe el derecho de hacer valer un copyright distinto en las
18 contribuciones hechas a nuestra comunidad, compartimos el interés de
20 de una manera que beneficia a nuestra comunidad y no tenga un indeseado
21 impacto negativo en la salud y crecimiento de nuestro ecosistema de software.
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
34 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
35 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
73 int ret = ctx->error; in tc358762_clear_error()
75 ctx->error = 0; in tc358762_clear_error()
81 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
85 if (ctx->error) in tc358762_write()
97 ctx->error = ret; in tc358762_write()
[all …]
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| D | tc358764.c | 1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
36 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
37 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
38 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
39 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
55 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
126 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/ |
| D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
35 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
36 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
52 #define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
96 if (ctx->error) in tc358762_write()
[all …]
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| D | tc358764.c | 1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
32 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
33 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
34 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
35 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
51 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
122 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
[all …]
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| /kernel/linux/linux-6.6/drivers/bus/ |
| D | qcom-ebi2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
75 * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
[all …]
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| /kernel/linux/linux-5.10/drivers/bus/ |
| D | qcom-ebi2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
75 * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
[all …]
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| /kernel/linux/linux-5.10/drivers/scsi/ufs/ |
| D | ufs-qcom.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 #include <linux/reset-controller.h>
26 /* vendor specific pre-defined parameters */
159 * Make sure assertion of ufs phy reset is written to in ufs_qcom_assert_reset()
171 * Make sure de-assertion of ufs phy reset is written to in ufs_qcom_deassert_reset()
239 if (host->hw_ver.major <= 0x02) in ufs_qcom_get_debug_reg_offset()
253 if (host->caps & UFS_QCOM_CAP_QUNIPRO) in ufs_qcom_cap_qunipro()
259 /* ufs-qcom-ice.c */
|
| /kernel/linux/linux-6.6/Documentation/process/ |
| D | kernel-enforcement-statement.rst | 4 ----------------------------------
8 reciprocal sharing obligations of GPL-2.0 is critical to the long-term
20 Notwithstanding the termination provisions of the GPL-2.0, we agree that
22 following provisions of GPL-3.0 as additional permissions under our
23 license with respect to any non-defensive assertion of rights under the
48 Finally, once a non-compliance issue is resolved, we hope the user will feel
55 - Laura Abbott
56 - Bjorn Andersson (Linaro)
57 - Andrea Arcangeli
58 - Neil Armstrong
[all …]
|
| /kernel/linux/linux-5.10/Documentation/process/ |
| D | kernel-enforcement-statement.rst | 4 ----------------------------------
8 reciprocal sharing obligations of GPL-2.0 is critical to the long-term
20 Notwithstanding the termination provisions of the GPL-2.0, we agree that
22 following provisions of GPL-3.0 as additional permissions under our
23 license with respect to any non-defensive assertion of rights under the
48 Finally, once a non-compliance issue is resolved, we hope the user will feel
55 - Laura Abbott
56 - Bjorn Andersson (Linaro)
57 - Andrea Arcangeli
58 - Neil Armstrong
[all …]
|
| /kernel/linux/linux-5.10/Documentation/scsi/ |
| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
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| /kernel/linux/linux-6.6/Documentation/scsi/ |
| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
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| /kernel/linux/linux-5.10/drivers/rtc/ |
| D | rtc-jz4740.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
66 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
78 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
94 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); in jz4780_rtc_enable_write()
96 return timeout ? 0 : -EIO; in jz4780_rtc_enable_write()
104 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
[all …]
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| /kernel/linux/linux-6.6/drivers/rtc/ |
| D | rtc-jz4740.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
[all …]
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