| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen()
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
42 regmap_write(adv->regmap_cec, 0x16, in adv7511_dsi_config_timing_gen()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen()
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
42 regmap_write(adv->regmap_cec, 0x16, in adv7511_dsi_config_timing_gen()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
45 /* Trigger Source Select - ASIC-defendant, actual values for the
74 /* Trigger Source Select - ASIC-dependant, actual values for the
126 /* determine if given timing can be supported by TG */
129 const struct dc_crtc_timing *timing,
134 /* Program timing generator with given timing */
139 /* Disable/Enable Timing Generator */
166 /*********** Timing Generator Synchronization routines ****/
188 /* disabling trigger-reset */
200 /* Fully program CRTC timing in timing generator */
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| D | dce110_timing_generator.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
49 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
55 * So we can create dce110 timing generator to use it.
67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
45 /* Trigger Source Select - ASIC-defendant, actual values for the
74 /* Trigger Source Select - ASIC-dependant, actual values for the
126 /* determine if given timing can be supported by TG */
129 const struct dc_crtc_timing *timing,
134 /* Program timing generator with given timing */
139 /* Disable/Enable Timing Generator */
166 /*********** Timing Generator Synchronization routines ****/
188 /* disabling trigger-reset */
200 /* Fully program CRTC timing in timing generator */
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| D | dce110_timing_generator.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
49 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
55 * So we can create dce110 timing generator to use it.
67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_optc.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
34 optc1->tg_regs->reg
37 optc1->base.ctx
41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
44 struct dc_crtc_timing *timing) in optc31_set_odm_combine() argument
47 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) in optc31_set_odm_combine()
90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
91 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
95 * Enable CRTC - call ASIC Control Object to enable Timing generator.
103 OPTC_SEG0_SRC_SEL, optc->inst); in optc31_enable_crtc()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
33 optc1->tg_regs->reg
36 optc1->base.ctx
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
45 * apply_front_porch_workaround() - This is a workaround for a bug that has
50 * @timing: Timing parameters used to configure DCN blocks.
52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) in apply_front_porch_workaround() argument
54 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
55 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
56 timing->v_front_porch = 2; in apply_front_porch_workaround()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/geode/ |
| D | display_gx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The number of pages is (PMAX - PMIN)+1 */ in gx_frame_buffer_size()
33 val -= (lo & 0x000fffff); in gx_frame_buffer_size()
59 struct gxfb_par *par = info->par; in gx_set_mode()
70 /* Disable the timing generator. */ in gx_set_mode()
77 /* Disable FIFO load and compression. */ in gx_set_mode()
102 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); in gx_set_mode()
104 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2); in gx_set_mode()
112 switch (info->var.bits_per_pixel) { in gx_set_mode()
125 /* Enable timing generator. */ in gx_set_mode()
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| D | display_gx1.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * -- Geode GX1 display controller
58 return -ENOMEM; in gx1_frame_buffer_size()
74 return dram_size - fb_base; in gx1_frame_buffer_size()
79 struct geodefb_par *par = info->par; in gx1_set_mode()
85 readl(par->dc_regs + DC_UNLOCK); in gx1_set_mode()
86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
88 gcfg = readl(par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
89 tcfg = readl(par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
91 /* Blank the display and disable the timing generator. */ in gx1_set_mode()
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| /kernel/linux/linux-6.6/drivers/video/fbdev/geode/ |
| D | display_gx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The number of pages is (PMAX - PMIN)+1 */ in gx_frame_buffer_size()
33 val -= (lo & 0x000fffff); in gx_frame_buffer_size()
59 struct gxfb_par *par = info->par; in gx_set_mode()
70 /* Disable the timing generator. */ in gx_set_mode()
77 /* Disable FIFO load and compression. */ in gx_set_mode()
102 write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); in gx_set_mode()
104 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2); in gx_set_mode()
112 switch (info->var.bits_per_pixel) { in gx_set_mode()
125 /* Enable timing generator. */ in gx_set_mode()
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| D | display_gx1.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * -- Geode GX1 display controller
58 return -ENOMEM; in gx1_frame_buffer_size()
74 return dram_size - fb_base; in gx1_frame_buffer_size()
79 struct geodefb_par *par = info->par; in gx1_set_mode()
85 readl(par->dc_regs + DC_UNLOCK); in gx1_set_mode()
86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
88 gcfg = readl(par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
89 tcfg = readl(par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
91 /* Blank the display and disable the timing generator. */ in gx1_set_mode()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | adi,adv7533.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
20 - adi,adv7533
21 - adi,adv7535
35 reg-names:
38 needing a non-default address.
41 - const: main
42 - const: edid
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) in apply_front_porch_workaround() argument
51 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
52 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
53 timing->v_front_porch = 2; in apply_front_porch_workaround()
55 if (timing->v_front_porch < 1) in apply_front_porch_workaround()
56 timing->v_front_porch = 1; in apply_front_porch_workaround()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_optc.c | 1 // SPDX-License-Identifier: MIT
36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
47 * Enable CRTC - call ASIC Control Object to enable Timing generator.
51 struct dc_crtc_timing *timing) in optc314_set_odm_combine() argument
55 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; in optc314_set_odm_combine()
102 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
103 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
112 OPTC_SEG0_SRC_SEL, optc->inst); in optc314_enable_crtc()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | adi,adv7511.txt | 2 ------------------------------------------------
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as
45 - adi,input-justification: The input bit justification ("left", "evenly",
48 - avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
49 - dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_timing_generator.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
67 #define RxINT_DISAB 0 /* Rx Int Disable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
137 #define nDTRnREQ 0x10 /* /DTR/REQ timing */
146 #define DLC 4 /* Disable Lower Chain */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
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| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
67 #define RxINT_DISAB 0 /* Rx Int Disable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
137 #define nDTRnREQ 0x10 /* /DTR/REQ timing */
146 #define DLC 4 /* Disable Lower Chain */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_timing_generator.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_optc.c | 36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
46 struct dc_crtc_timing *timing) in optc32_set_odm_combine() argument
50 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; in optc32_set_odm_combine()
97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
98 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
109 * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
121 OPTC_SEG0_SRC_SEL, optc->inst); in optc32_enable_crtc()
155 /* disable otg request until end of the first line in optc32_disable_crtc()
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | cafe_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
92 static int timing[3]; variable
93 module_param_array(timing, int, &numtimings, 0644);
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", in cafe_device_ready()
124 if (cafe->usedma) in cafe_write_buf()
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); in cafe_write_buf()
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | cafe_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
92 static int timing[3]; variable
93 module_param_array(timing, int, &numtimings, 0644);
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", in cafe_device_ready()
124 if (cafe->usedma) in cafe_write_buf()
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); in cafe_write_buf()
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
101 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
105 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
118 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
127 hw->init = &init; in meson8b_dwmac_register_clk()
129 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
135 struct device *dev = dwmac->dev; in meson8b_init_rgmii_tx_clk()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
129 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
138 hw->init = &init; in meson8b_dwmac_register_clk()
140 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
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