Home
last modified time | relevance | path

Searched +full:dll +full:- +full:config (Results 1 – 25 of 88) sorted by relevance

1234

/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
140 /* Max load for eMMC Vdd-io supply */
146 /* Max load for SD Vdd-io supply */
150 msm_host->var_ops->msm_readl_relaxed(host, offset)
153 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
[all …]
Dsdhci-esdhc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* pltfm-specific */
89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
128 /* Offset of DLL Control register */
132 /* DLL Update Enable bit */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
[all …]
Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
90 /* TOP config registers to manage static and dynamic delay */
102 /* register to provide the phase-shift value for DLL */
119 * DLL procedure has finished before switching to ultra-speed modes.
139 * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
145 struct mmc_host *mhost = host->mmc; in st_mmcss_cconfig()
148 if (!of_device_is_compatible(np, "st,sdhci-stih407")) in st_mmcss_cconfig()
[all …]
Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
73 /* dll control register */
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
84 /* strobe dll register */
140 * open ended multi-blk IO. Otherwise the TC INT wouldn't
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
21 #include "sdhci-pltfm.h"
120 #define INVALID_TUNING_PHASE -1
134 /* Max load for eMMC Vdd-io supply */
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
295 return msm_host->offset; in sdhci_priv_msm_offset()
308 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
[all …]
Dsdhci-esdhc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* pltfm-specific */
89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
16 #include "sdhci-pltfm.h"
17 #include "sdhci-xenon.h"
125 /* Offset of DLL Control register */
129 /* DLL Update Enable bit */
206 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
208 return -ENOMEM; in xenon_alloc_emmc_phy()
210 priv->phy_params = params; in xenon_alloc_emmc_phy()
211 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
[all …]
Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
90 /* TOP config registers to manage static and dynamic delay */
102 /* register to provide the phase-shift value for DLL */
119 * DLL procedure has finished before switching to ultra-speed modes.
139 * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
145 struct mmc_host *mhost = host->mmc; in st_mmcss_cconfig()
148 if (!of_device_is_compatible(np, "st,sdhci-stih407")) in st_mmcss_cconfig()
[all …]
Ddw_mmc-zx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 #include "dw_mmc-pltfm.h"
22 #include "dw_mmc-zx.h"
36 struct dw_mci_zx_priv_data *priv = host->priv; in dw_mci_zx_emmc_set_delay()
37 struct regmap *sysc_base = priv->sysc_base; in dw_mci_zx_emmc_set_delay()
43 return -EINVAL; in dw_mci_zx_emmc_set_delay()
78 } while (--loop && !(clksel & ZX_DLL_LOCKED)); in dw_mci_zx_emmc_set_delay()
81 dev_err(host->dev, "Error: %s dll lock fail\n", __func__); in dw_mci_zx_emmc_set_delay()
82 return -EIO; in dw_mci_zx_emmc_set_delay()
90 struct dw_mci *host = slot->host; in dw_mci_zx_emmc_execute_tuning()
[all …]
Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
27 #include <linux/platform_data/mmc-esdhc-imx.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
74 /* dll control register */
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
85 /* strobe dll register */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
[all …]
/kernel/uniproton/demos/hi3093/bsp/uart/
Duart.c2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * Create: 2009-12-22
27 void calc_uart_dll_dlh(U32 uartclk, U32 baudrate, U32 *dll, U32 *dlh) in calc_uart_dll_dlh() argument
35 *dll = divisor & 0xFF; in calc_uart_dll_dlh()
43 switch (cfg->data_bits) { in calc_lcr_reg_val()
61 /* 0 - 1 stop bit 1 - 2 stop bit */ in calc_lcr_reg_val()
62 if (cfg->stop == 2) { in calc_lcr_reg_val()
66 if (cfg->pen) { in calc_lcr_reg_val()
68 if (cfg->eps) { in calc_lcr_reg_val()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
122 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
122 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-orion5x/
Dtsx09-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * QNAP TS-x09 Boards common functions
15 #include "tsx09-common.h"
19 * QNAP TS-x09 specific power off method via UART1-attached PIC
29 pr_info("%s: triggering power-off...\n", __func__); in qnap_tsx09_power_off()
33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
40 /* send the power-off command 'A' to PIC */ in qnap_tsx09_power_off()
55 return n - '0'; in qnap_tsx09_parse_hex_nibble()
58 return n - 'A' + 10; in qnap_tsx09_parse_hex_nibble()
61 return n - 'a' + 10; in qnap_tsx09_parse_hex_nibble()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-orion5x/
Dtsx09-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * QNAP TS-x09 Boards common functions
15 #include "tsx09-common.h"
19 * QNAP TS-x09 specific power off method via UART1-attached PIC
29 pr_info("%s: triggering power-off...\n", __func__); in qnap_tsx09_power_off()
33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
40 /* send the power-off command 'A' to PIC */ in qnap_tsx09_power_off()
55 return n - '0'; in qnap_tsx09_parse_hex_nibble()
58 return n - 'A' + 10; in qnap_tsx09_parse_hex_nibble()
61 return n - 'a' + 10; in qnap_tsx09_parse_hex_nibble()
[all …]
/kernel/linux/linux-6.6/include/linux/ssb/
Dssb_driver_gige.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
29 #define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
62 return container_of(pdev->bus->ops, struct ssb_gige, pci_ops); in pdev_to_ssb_gige()
69 return (dev ? dev->has_rgmii : 0); in ssb_gige_is_rgmii()
77 return !!(dev->dev->bus->sprom.boardflags_lo & in ssb_gige_have_roboswitch()
87 return ((dev->dev->bus->chip_id == 0x4785) && in ssb_gige_one_dma_at_once()
88 (dev->dev->bus->chip_rev < 2)); in ssb_gige_one_dma_at_once()
97 return (dev->dev->bus->chip_id == 0x4785); in ssb_gige_must_flush_posted_writes()
[all …]
/kernel/linux/linux-5.10/include/linux/ssb/
Dssb_driver_gige.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
29 #define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
62 return container_of(pdev->bus->ops, struct ssb_gige, pci_ops); in pdev_to_ssb_gige()
69 return (dev ? dev->has_rgmii : 0); in ssb_gige_is_rgmii()
77 return !!(dev->dev->bus->sprom.boardflags_lo & in ssb_gige_have_roboswitch()
87 return ((dev->dev->bus->chip_id == 0x4785) && in ssb_gige_one_dma_at_once()
88 (dev->dev->bus->chip_rev < 2)); in ssb_gige_one_dma_at_once()
97 return (dev->dev->bus->chip_id == 0x4785); in ssb_gige_must_flush_posted_writes()
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-nxp-fspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2019-2020 NXP
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
58 #include <linux/spi/spi-mem.h>
300 #define LUT_PAD(x) (fls(x) - 1)
306 * ---------------------------------------------------
[all …]
Dspi-cadence-xspi.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2020-21 Cadence
18 #include <linux/spi/spi-mem.h>
25 #define CDNS_XSPI_NAME "cadence-xspi"
29 * configure XSPI controller pin-strap settings
41 /* PHY DLL slave control register */
44 /* DLL PHY control register */
91 /* Controller config register */
155 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
158 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/microchip/
Dlan937x_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
71 if (!dev->info->internal_phy[addr]) in lan937x_internal_phy_write()
72 return -EOPNOTSUPP; in lan937x_internal_phy_write()
93 dev_err(dev->dev, "Failed to write phy register\n"); in lan937x_internal_phy_write()
106 /* Check for internal phy port, return 0xffff for non-existent phy */ in lan937x_internal_phy_read()
107 if (!dev->info->internal_phy[addr]) in lan937x_internal_phy_read()
123 dev_err(dev->dev, "Failed to read phy register\n"); in lan937x_internal_phy_read()
174 const u32 *masks = dev->info->masks; in lan937x_port_setup()
175 const u16 *regs = dev->info->regs; in lan937x_port_setup()
[all …]
/kernel/linux/linux-6.6/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
108 int res = -1; in cvmx_spi_start_interface()
[all …]
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
108 int res = -1; in cvmx_spi_start_interface()
[all …]

1234