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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dmediatek,uart-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
17 - $ref: dma-controller.yaml#
22 - items:
23 - enum:
24 - mediatek,mt2712-uart-dma
[all …]
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
55 33: SPI controller 2
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dmtk-uart-apdma.txt4 - compatible should contain:
5 * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
6 * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
8 - reg: The base address of the APDMA register bank.
10 - interrupts: A single interrupt specifier.
11 One interrupt per dma-requests, or 8 if no dma-requests property is present
13 - dma-requests: The number of DMA channels
15 - clocks : Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names: The APDMA clock for register accesses
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-fb.txt6 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7 - reg : Should contain 1 register ranges(address and length)
8 - interrupts : One interrupt of the fb dev
11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
14 - bits-per-pixel: Bits per pixel
15 - fsl,pcr: LCDC PCR value
17 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
20 - lcd-supply: Regulator for LCD supply voltage.
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); in pdc202xx_exec_command()
43 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
49 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
53 if (ap->port_no) { in pdc202xx_irq_check()
69 * pdc202xx_configure_piomode - set chip PIO timing
81 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_configure_piomode()
[all …]
Dpata_optidma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_optidma.c - Opti DMA PATA for new ATA layer
6 * The Opti DMA controllers are related to the older PIO PCI controllers
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
13 * These devices support virtual DMA for read (aka the CS5520). Later
15 * so you have to get this right. We don't support the virtual DMA
18 * Bits that are worth knowing
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
45 static int pci_clock; /* 0 = 33 1 = 25 */
[all …]
Dpata_sc1200.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * TODO: Needs custom DMA cleanup code
10 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003
12 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
37 * sc1200_clock - PCI clock
40 * in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
51 return 0; /* 33 MHz mode */ in sc1200_clock()
54 0/3 is 33Mhz 1 is 48 2 is 66 */ in sc1200_clock()
65 * sc1200_set_piomode - PIO setup
75 /* format0, 33Mhz */ in sc1200_set_piomode()
[all …]
/kernel/linux/linux-6.6/drivers/ata/
Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
51 if (ap->port_no) { in pdc202xx_irq_check()
67 * pdc202xx_configure_piomode - set chip PIO timing
79 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_configure_piomode()
80 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; in pdc202xx_configure_piomode()
[all …]
Dpata_optidma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_optidma.c - Opti DMA PATA for new ATA layer
6 * The Opti DMA controllers are related to the older PIO PCI controllers
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
13 * These devices support virtual DMA for read (aka the CS5520). Later
15 * so you have to get this right. We don't support the virtual DMA
18 * Bits that are worth knowing
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
45 static int pci_clock; /* 0 = 33 1 = 25 */
[all …]
Dpata_sc1200.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * TODO: Needs custom DMA cleanup code
10 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003
12 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
37 * sc1200_clock - PCI clock
40 * in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
51 return 0; /* 33 MHz mode */ in sc1200_clock()
54 0/3 is 33Mhz 1 is 48 2 is 66 */ in sc1200_clock()
65 * sc1200_set_piomode - PIO setup
75 /* format0, 33Mhz */ in sc1200_set_piomode()
[all …]
Dpata_cypress.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_cypress.c - Cypress PATA for new ATA layer
46 MODULE_PARM_DESC(enable_dma, "Enable bus master DMA operations");
49 * cy82c693_set_piomode - set initial PIO mode data
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cy82c693_set_piomode()
60 const unsigned long T = 1000000 / 33; in cy82c693_set_piomode()
64 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) { in cy82c693_set_piomode()
69 time_16 = clamp_val(t.recover - 1, 0, 15) | in cy82c693_set_piomode()
70 (clamp_val(t.active - 1, 0, 15) << 4); in cy82c693_set_piomode()
71 time_8 = clamp_val(t.act8b - 1, 0, 15) | in cy82c693_set_piomode()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/pxa/
Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-channels = <32>;
16 #dma-cells = <2>;
17 #dma-requests = <75>;
21 pxairq: interrupt-controller@40d00000 {
22 marvell,intc-priority;
23 marvell,intc-nr-irqs = <34>;
[all …]
Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
[all …]
/kernel/linux/linux-5.10/drivers/ide/
Dsc1200.c2 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
54 // the clock is in bits 8 and 9 of this word in sc1200_get_pci_clock()
66 * Here are the standard PIO mode 0-4 timings for each "format".
67 * Format-0 uses fast data reg timings, with slower command reg timings.
68 * Format-1 uses fast timings for all registers, but won't work with all drives.
71 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
72 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
83 ide_hwif_t *hwif = drive->hwif; in sc1200_tunepio()
84 struct pci_dev *pdev = to_pci_dev(hwif->dev); in sc1200_tunepio()
85 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; in sc1200_tunepio()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/davinci/
Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
[all …]
/kernel/linux/linux-5.10/arch/sparc/kernel/
Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
34 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
35 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
36 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
37 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
38 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
40 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
44 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
45 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
[all …]
/kernel/linux/linux-6.6/arch/sparc/kernel/
Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
34 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
35 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
36 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
37 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
38 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
40 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
44 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
45 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dvirtio_config.h49 * Virtio feature bits VIRTIO_TRANSPORT_F_START through
52 * rest are per-device feature bits.
70 * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature.
71 * If set - use platform DMA tools to access the memory.
76 #define VIRTIO_F_ACCESS_PLATFORM 33
/kernel/linux/linux-6.6/arch/powerpc/include/asm/nohash/32/
Dpte-85xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
14 - PRESENT *must* be in the bottom two bits because swap PTEs use
15 the top 30 bits.
19 /* Definitions for FSL Book-E Cores */
52 * We define 2 sets of base prot bits, one for basic pages (ie,
55 * the processor might need it for DMA coherency.
/kernel/linux/linux-5.10/arch/powerpc/include/asm/nohash/32/
Dpte-fsl-booke.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
14 - PRESENT *must* be in the bottom three bits because swap cache
15 entries use the top 29 bits.
19 /* Definitions for FSL Book-E Cores */
52 * We define 2 sets of base prot bits, one for basic pages (ie,
55 * the processor might need it for DMA coherency.
/kernel/linux/linux-6.6/include/uapi/linux/
Dvirtio_config.h49 * Virtio feature bits VIRTIO_TRANSPORT_F_START through
52 * rest are per-device feature bits.
70 * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature.
71 * If set - use platform DMA tools to access the memory.
76 #define VIRTIO_F_ACCESS_PLATFORM 33
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
[all …]

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