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/kernel/linux/linux-5.10/drivers/scsi/
Dzorro_esp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ESP front-end for Amiga ZORRO SCSI systems.
11 * Blizzard 1230 DMA and probe function fixes
24 * Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
32 #include <linux/dma-mapping.h>
55 /* per-board register layout definitions */
57 /* Blizzard 1230 DMA interface */
60 unsigned char dma_addr; /* DMA address [0x0000] */
62 unsigned char dma_latch; /* DMA latch [0x8000] */
65 /* Blizzard 1230II DMA interface */
[all …]
/kernel/linux/linux-6.6/drivers/scsi/
Dzorro_esp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ESP front-end for Amiga ZORRO SCSI systems.
11 * Blizzard 1230 DMA and probe function fixes
24 * Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
32 #include <linux/dma-mapping.h>
55 /* per-board register layout definitions */
57 /* Blizzard 1230 DMA interface */
60 unsigned char dma_addr; /* DMA address [0x0000] */
62 unsigned char dma_latch; /* DMA latch [0x8000] */
65 /* Blizzard 1230II DMA interface */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt3 Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
[all …]
Dk3dma.txt1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt3 Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
[all …]
Dk3dma.txt1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
[all …]
Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lightning Mountain centralized DMA controllers.
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
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/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
Drtl8723b_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
10 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
59 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
77 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
80 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
81 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
87 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
190 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
199 #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */
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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
Drtl8723b_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
12 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
61 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
79 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
82 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
83 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
89 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
202 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
211 #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Ddma-buf.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * struct dma_buf_sync - Synchronize with CPU access.
28 * When a DMA buffer is accessed from the CPU via mmap, it is not always
29 * possible to guarantee coherency between the CPU-visible map and underlying
35 * with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
37 * DMA_BUF_SYNC_END and the same read/write flags.
45 * follow-up work is not submitted to GPU or other device driver until
50 * poll() on the DMA buffer file descriptor. If the driver or API requires
52 * other synchronization primitive outside the scope of the DMA buffer API.
65 * Indicates that the mapped DMA buffer will be read by the
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpu/host1x/
Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
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/kernel/linux/linux-6.6/sound/mips/
Dhal2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
39 /* 1=DMA Port */
40 /* 9=Global DMA Control */
46 /* If IAR_TYPE_M=DMA Port: */
53 /* If IAR_TYPE_M=Global DMA Control: */
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
[all …]
/kernel/linux/linux-5.10/sound/mips/
Dhal2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
39 /* 1=DMA Port */
40 /* 9=Global DMA Control */
46 /* If IAR_TYPE_M=DMA Port: */
53 /* If IAR_TYPE_M=Global DMA Control: */
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/52xx/
Dmpc52xx_lpbfifo.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * - Add support for multiple requests to be queued.
60 * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transferred
64 size_t transfer_size = req->size - req->pos; in mpc52xx_lpbfifo_kick()
70 int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA); in mpc52xx_lpbfifo_kick() local
71 int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE; in mpc52xx_lpbfifo_kick() local
72 int poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA; in mpc52xx_lpbfifo_kick()
79 if (!dma) { in mpc52xx_lpbfifo_kick()
81 * 16M-1, the FIFO itself is only 512 bytes deep and it does in mpc52xx_lpbfifo_kick()
93 if (write) { in mpc52xx_lpbfifo_kick()
[all …]
/kernel/linux/linux-6.6/include/linux/dma/
Dedma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
30 * struct dw_edma_core_ops - platform-specific eDMA methods
32 * method accepts the channel id in the end-to-end
33 * numbering with the eDMA write channels being placed
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
67 * @nr_irqs: total number of DMA IRQs
68 * @ops DMA channel to IRQ number mapping
70 * @reg_base DMA register base address
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
[all …]
/kernel/linux/linux-6.6/drivers/mtd/nand/raw/
Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
DHal8723BReg.h1 /* SPDX-License-Identifier: GPL-2.0 */
152 #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELE…
153 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
177 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
180 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
181 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
187 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
265 /* Format for offset 540h-542h: */
272 /* |<--Setup--|--Hold------------>| */
273 /* --------------|---------------------- */
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
DHal8723BReg.h1 /* SPDX-License-Identifier: GPL-2.0 */
149 #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_REL…
150 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
173 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
176 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
177 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
183 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
261 /* Format for offset 540h-542h: */
268 /* |<--Setup--|--Hold------------>| */
269 /* --------------|---------------------- */
[all …]
/kernel/linux/linux-5.10/drivers/dma/dw-edma/
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma/edma.h>
18 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
51 INIT_LIST_HEAD(&burst->list); in dw_edma_alloc_burst()
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-at91-master.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
18 #include <linux/dma-mapping.h>
29 #include <linux/platform_data/dma-atmel.h>
32 #include "i2c-at91.h"
36 struct at91_twi_pdata *pdata = dev->pdata; in at91_init_twi_bus_master()
40 if (dev->fifo_size) in at91_init_twi_bus_master()
44 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); in at91_init_twi_bus_master()
47 if (pdata->has_dig_filtr && dev->enable_dig_filt) in at91_init_twi_bus_master()
51 if (pdata->has_adv_dig_filtr && dev->enable_dig_filt) in at91_init_twi_bus_master()
[all …]
/kernel/linux/linux-6.6/Documentation/PCI/
Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
4 How To Write Linux PCI Drivers
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
[all …]
/kernel/linux/linux-5.10/Documentation/PCI/
Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
4 How To Write Linux PCI Drivers
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
[all …]
/kernel/linux/linux-6.6/drivers/i2c/busses/
Di2c-at91-master.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
18 #include <linux/dma-mapping.h>
30 #include "i2c-at91.h"
34 struct at91_twi_pdata *pdata = dev->pdata; in at91_init_twi_bus_master()
38 if (dev->fifo_size) in at91_init_twi_bus_master()
42 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); in at91_init_twi_bus_master()
45 if (pdata->has_dig_filtr && dev->enable_dig_filt) in at91_init_twi_bus_master()
49 if (pdata->has_adv_dig_filtr && dev->enable_dig_filt) in at91_init_twi_bus_master()
51 (AT91_TWI_FILTR_THRES(dev->filter_width) & in at91_init_twi_bus_master()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
[all …]

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