Home
last modified time | relevance | path

Searched +full:dp +full:- +full:phy (Results 1 – 25 of 496) sorted by relevance

12345678910>>...20

/kernel/linux/linux-6.6/drivers/phy/rockchip/
Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
[all …]
/kernel/linux/linux-5.10/drivers/phy/rockchip/
Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-usb43dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
[all …]
Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common PHY and network PCS transmit amplitude property
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
20 contains multiple values for various PHY modes, the
[all …]
Dsamsung,dp-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC DisplayPort PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
[all …]
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
28 #include <linux/phy/phy.h>
39 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
46 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
181 /* PHY configuration and status registers */
241 * struct zynqmp_dp_link_config - Common link config between source and sink
251 * struct zynqmp_dp_mode - Configured mode of DisplayPort
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
31 #include <linux/phy/phy.h>
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
182 /* PHY configuration and status registers */
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
[all …]
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Danalogix_dp.txt3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
16 -clock-names:
[all …]
/kernel/linux/linux-6.6/drivers/phy/mediatek/
Dphy-mtk-dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek DisplayPort PHY driver
13 #include <linux/phy/phy.h>
85 static int mtk_dp_phy_init(struct phy *phy) in mtk_dp_phy_init() argument
87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init()
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init()
101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init()
103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init()
109 static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) in mtk_dp_phy_configure() argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/
Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
12 #include <linux/phy/phy.h>
16 #include <sound/hdmi-codec.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
61 { .compatible = "rockchip,rk3399-cdn-dp",
68 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
73 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
75 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
12 #include <linux/phy/phy.h>
16 #include <sound/hdmi-codec.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
55 { .compatible = "rockchip,rk3399-cdn-dp",
62 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
67 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
69 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
[all …]
/kernel/linux/linux-6.6/drivers/phy/samsung/
Dphy-exynos-dp-video.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series Display Port PHY driver
15 #include <linux/phy/phy.h>
18 #include <linux/soc/samsung/exynos-regs-pmu.h>
29 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument
31 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on()
33 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
34 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
38 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument
40 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off()
[all …]
/kernel/linux/linux-5.10/drivers/phy/samsung/
Dphy-exynos-dp-video.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series Display Port PHY driver
17 #include <linux/phy/phy.h>
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
31 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument
33 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on()
35 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
36 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
40 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument
42 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
20 msm-$(CONFIG_DRM_MSM_HDMI) += \
33 msm-$(CONFIG_DRM_MSM_MDP4) += \
44 msm-$(CONFIG_DRM_MSM_MDP5) += \
57 msm-$(CONFIG_DRM_MSM_DPU) += \
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
99 msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
100 dp/dp_debug.o
102 msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
104 msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
Ddp_parser.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
10 #include <linux/phy/phy.h>
11 #include <linux/phy/phy-dp.h>
15 #define DP_LABEL "MDSS DP DISPLAY"
52 * struct dp_display_data - display related device tree data.
55 * @phy_node: reference to phy device
69 * struct dp_ctrl_resource - controller's IO related data
72 * @phy_io: phy's mapped memory address
76 struct phy *phy; member
[all …]
/kernel/linux/linux-6.6/net/dsa/
Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2017 Savoir-faire Linux Inc.
22 * dsa_port_notify - Notify the switching fabric of changes to a port
23 * @dp: port on which change occurred
25 * @v: event-specific value.
29 * reconfigure themselves for cross-chip operations. Can also be used to
33 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument
35 return dsa_tree_notify(dp->ds->dst, e, v); in dsa_port_notify()
38 static void dsa_port_notify_bridge_fdb_flush(const struct dsa_port *dp, u16 vid) in dsa_port_notify_bridge_fdb_flush() argument
40 struct net_device *brport_dev = dsa_port_to_bridge_port(dp); in dsa_port_notify_bridge_fdb_flush()
[all …]

12345678910>>...20