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/kernel/linux/linux-5.10/drivers/phy/cadence/
Dcdns-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
16 #include <linux/phy/phy-mipi-dphy.h>
21 /* DPHY registers */
76 int (*probe)(struct cdns_dphy *dphy);
77 void (*remove)(struct cdns_dphy *dphy);
78 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
79 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
80 enum cdns_dphy_clk_lane_cfg cfg);
81 void (*set_pll_cfg)(struct cdns_dphy *dphy,
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/kernel/linux/linux-6.6/drivers/phy/cadence/
Dcdns-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
17 #include <linux/phy/phy-mipi-dphy.h>
23 /* DPHY registers */
94 int (*probe)(struct cdns_dphy *dphy);
95 void (*remove)(struct cdns_dphy *dphy);
96 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
97 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
98 enum cdns_dphy_clk_lane_cfg cfg);
99 void (*set_pll_cfg)(struct cdns_dphy *dphy,
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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Dstarfive,jh7110-dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
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/kernel/linux/linux-5.10/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
19 /* DPHY registers */
47 ((x) < 32) ? 0xe0 | ((x) - 16) : \
48 ((x) < 64) ? 0xc0 | ((x) - 32) : \
49 ((x) < 128) ? 0x80 | ((x) - 64) : \
50 ((x) - 128))
51 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
52 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
81 /* DPHY PLL parameters */
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/kernel/linux/linux-6.6/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
35 /* DPHY registers */
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
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/kernel/linux/linux-5.10/drivers/staging/media/rkisp1/
Drkisp1-isp.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - ISP Subdevice
13 #include <linux/phy/phy-mipi-dphy.h>
17 #include <media/v4l2-event.h>
19 #include "rkisp1-common.h"
40 * +---------------------------------------------------------+
42 * | +---------------------------------------------------+ |
45 * | | +--------------------------------------------+ | |
48 * | | | +---------------------------------+ | | |
51 * | | | +---------------------------------+ | | |
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Drkisp1-common.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Rockchip ISP1 Driver - Common definitions
16 #include <media/media-device.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/videobuf2-v4l2.h>
22 #include "rkisp1-regs.h"
23 #include "uapi/rkisp1-config.h"
92 * struct rkisp1_sensor_async - A container for the v4l2_async_subdev to add to the notifier
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/kernel/linux/linux-6.6/drivers/phy/starfive/
Dphy-jh7110-dphy-rx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 DPHY RX driver
80 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
81 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
89 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | in stf_dphy_configure()
90 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | in stf_dphy_configure()
91 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | in stf_dphy_configure()
92 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), in stf_dphy_configure()
93 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
95 writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | in stf_dphy_configure()
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/kernel/linux/linux-6.6/drivers/gpu/drm/kmb/
Dkmb_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
178 clk_disable_unprepare(kmb_dsi->clk_mipi); in kmb_dsi_clk_disable()
179 clk_disable_unprepare(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_disable()
180 clk_disable_unprepare(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_disable()
186 mipi_dsi_host_unregister(kmb_dsi->host); in kmb_dsi_host_unregister()
225 return -ENOMEM; in kmb_dsi_host_bridge_init()
227 dsi_host->ops = &kmb_dsi_host_ops; in kmb_dsi_host_bridge_init()
233 return -ENOMEM; in kmb_dsi_host_bridge_init()
237 dsi_host->dev = dev; in kmb_dsi_host_bridge_init()
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Dkmb_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
12 /* MIPI TX CFG */
18 /* DPHY Tx test codes*/
43 /* DPHY params */
58 /* 2 Data Lanes per D-PHY */
81 /* DPHY Tx test codes */
341 writel(value, (kmb_dsi->mipi_mmio + reg)); in kmb_write_mipi()
346 return readl(kmb_dsi->mipi_mmio + reg); in kmb_read_mipi()
354 u32 mask = (1 << num_bits) - 1; in kmb_write_bits_mipi()
/kernel/linux/linux-6.6/drivers/media/platform/rockchip/rkisp1/
Drkisp1-csi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - CSI-2 Receiver
16 #include <linux/phy/phy-mipi-dphy.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-fwnode.h>
21 #include "rkisp1-common.h"
22 #include "rkisp1-csi.h"
39 .pads = csi->pad_cfg in rkisp1_csi_get_pad_fmt()
42 lockdep_assert_held(&csi->lock); in rkisp1_csi_get_pad_fmt()
45 return v4l2_subdev_get_try_format(&csi->sd, sd_state, pad); in rkisp1_csi_get_pad_fmt()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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/kernel/linux/linux-6.6/drivers/phy/rockchip/
Dphy-rockchip-inno-dsidphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
12 #include <linux/clk-provider.h>
24 #include <linux/phy/phy-mipi-dphy.h>
290 orig = readl(inno->phy_base + reg); in phy_update_bits()
293 writel(tmp, inno->phy_base + reg); in phy_update_bits()
299 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
310 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
343 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate()
358 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
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Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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/kernel/linux/linux-5.10/drivers/phy/rockchip/
Dphy-rockchip-inno-dsidphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
11 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
213 orig = readl(inno->phy_base + reg); in phy_update_bits()
216 writel(tmp, inno->phy_base + reg); in phy_update_bits()
222 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
233 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
266 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate()
281 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
[all …]
Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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/kernel/linux/linux-6.6/drivers/phy/
Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
18 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
20 * of the D-PHY specification (v2.1).
25 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_get_default_config() argument
30 if (!cfg) in phy_mipi_dphy_get_default_config()
31 return -EINVAL; in phy_mipi_dphy_get_default_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_get_default_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
41 cfg->clk_pre = 8000; in phy_mipi_dphy_get_default_config()
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
85 * 2. Configure DSI Host and DPHY and enable DPHY
136 int ret = dsi->error; in nwl_dsi_clear_error()
138 dsi->error = 0; in nwl_dsi_clear_error()
146 if (dsi->error) in nwl_dsi_write()
149 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
151 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
154 dsi->error = ret; in nwl_dsi_write()
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/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
79 * 2. Configure DSI Host and DPHY and enable DPHY
130 int ret = dsi->error; in nwl_dsi_clear_error()
132 dsi->error = 0; in nwl_dsi_clear_error()
140 if (dsi->error) in nwl_dsi_write()
143 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
145 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0031_linux_drivers_perf_phy_pinctrl_ptp_pwm.patch7 Change-Id: I50a0069a60f92f57dd6112f6a9700811be19e564
9 diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
11 --- a/drivers/perf/fsl_imx8_ddr_perf.c
13 @@ -5,6 +5,7 @@
21 @@ -14,12 +15,15 @@
37 @@ -28,9 +32,18 @@
56 @@ -40,32 +53,56 @@
80 -static const struct fsl_ddr_devtype_data imx8_devtype_data;
106 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
107 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
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/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
332 u8 lanes_mask = GENMASK(device->lanes - 1, 0); in sun6i_dsi_inst_init()
359 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), in sun6i_dsi_inst_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
332 u8 lanes_mask = GENMASK(device->lanes - 1, 0); in sun6i_dsi_inst_init()
359 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), in sun6i_dsi_inst_init()
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