| /kernel/linux/linux-6.6/drivers/phy/starfive/ |
| D | phy-jh7110-dphy-rx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 DPHY RX driver
80 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
81 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
89 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | in stf_dphy_configure()
90 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | in stf_dphy_configure()
91 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | in stf_dphy_configure()
92 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), in stf_dphy_configure()
93 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
95 writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | in stf_dphy_configure()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
16 phy-jh7110-dphy-rx.ko.
26 phy-jh7110-pcie.ko.
36 phy-jh7110-usb.ko.
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) += phy-jh7110-dphy-rx.o
3 obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
4 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
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| /kernel/linux/linux-6.6/drivers/phy/cadence/ |
| D | cdns-dphy-rx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
13 #include <linux/phy/phy-mipi-dphy.h>
81 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_on() local
83 /* Start RX state machine. */ in cdns_dphy_rx_power_on()
87 dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_on()
94 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_off() local
96 writel(0, dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_off()
106 /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ in cdns_dphy_rx_get_band_ctrl()
110 return -EOPNOTSUPP; in cdns_dphy_rx_get_band_ctrl()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
3 obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
4 obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o
5 obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
6 obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
16 tristate "Cadence D-PHY Support"
21 Choose this option if you have a Cadence D-PHY in your
23 cdns-dphy.
26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | cdns,dphy-rx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DPHY Rx
10 - Pratyush Yadav <pratyush@kernel.org>
15 - const: cdns,dphy-rx
20 "#phy-cells":
23 power-domains:
27 - compatible
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| D | allwinner,sun6i-a31-mipi-dphy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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| D | starfive,jh7110-dphy-rx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
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| /kernel/linux/linux-6.6/drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include <linux/phy/phy-mipi-dphy.h>
21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
183 void (*tx_power_on)(struct sun6i_dphy *dphy);
202 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
204 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
205 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
206 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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| D | phy-rockchip-inno-csidphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip MIPI RX Innosilicon DPHY driver
17 #include <linux/phy/phy-mipi-dphy.h>
60 /* Configure the count time of the THS-SETTLE by protocol. */
71 * The higher 16-bit of this register is used for write protection
93 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
145 const struct dphy_drv_data *drv_data = priv->drv_data; in write_grf_reg()
146 const struct dphy_reg *reg = &drv_data->grf_regs[index]; in write_grf_reg()
148 if (reg->offset) in write_grf_reg()
149 regmap_write(priv->grf, reg->offset, in write_grf_reg()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-subdev.h>
81 struct phy *dphy; member
107 csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
111 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
119 ret = phy_power_on(csi2rx->dphy); in csi2rx_configure_ext_dphy()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | nxp,imx8mq-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
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| D | cdns,csi2rx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MIPI-CSI2 RX controller
10 - Maxime Ripard <mripard@kernel.org>
13 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
19 - enum:
20 - starfive,jh7110-csi2rx
21 - const: cdns,csi2rx
28 - description: CSI2Rx system clock
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
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| /kernel/linux/linux-6.6/drivers/video/fbdev/mmp/hw/ |
| D | mmp_ctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
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| /kernel/linux/linux-5.10/drivers/video/fbdev/mmp/hw/ |
| D | mmp_ctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/amlogic/ |
| D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson AXG MIPI DPHY driver
48 * [0] enalbe the MIPI DPHY TxDDRClk.
97 /* [24] rx turn watch dog triggered.
98 * [23] rx esc watchdog triggered.
144 /* Watchdog for RX low power state no finished. */
188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init()
192 ret = reset_control_reset(priv->reset); in phy_meson_axg_mipi_dphy_init()
205 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in phy_meson_axg_mipi_dphy_configure()
209 ret = phy_configure(priv->analog, opts); in phy_meson_axg_mipi_dphy_configure()
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| /kernel/linux/linux-5.10/drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
71 struct phy *dphy; member
98 csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
102 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
112 ret = clk_prepare_enable(csi2rx->p_clk); in csi2rx_start()
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/allwinner/ |
| D | sunxi-d1s-t113.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | cdns,csi2rx.txt | 1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/cadence/ |
| D | cdns-dsi-core.c | 1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/phy/phy-mipi-dphy.h>
25 #include "cdns-dsi-core.h"
27 #include "cdns-dsi-j721e.h"
72 #define DATA_LANE_EN(x) BIT((x) - 1)
448 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
450 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
462 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
472 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
479 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in cdns_dsi_mode2cfg()
[all …]
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