| /kernel/linux/linux-5.10/drivers/phy/cadence/ |
| D | cdns-dphy.c | 16 #include <linux/phy/phy-mipi-dphy.h>
21 /* DPHY registers */
76 int (*probe)(struct cdns_dphy *dphy);
77 void (*remove)(struct cdns_dphy *dphy);
78 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
79 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
81 void (*set_pll_cfg)(struct cdns_dphy *dphy,
83 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
95 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, in cdns_dsi_get_dphy_pll_cfg() argument
100 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/cadence/ |
| D | cdns-dphy.c | 17 #include <linux/phy/phy-mipi-dphy.h>
23 /* DPHY registers */
94 int (*probe)(struct cdns_dphy *dphy);
95 void (*remove)(struct cdns_dphy *dphy);
96 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
97 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
99 void (*set_pll_cfg)(struct cdns_dphy *dphy,
101 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
119 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, in cdns_dsi_get_dphy_pll_cfg() argument
124 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
[all …]
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| D | cdns-dphy-rx.c | 13 #include <linux/phy/phy-mipi-dphy.h>
81 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_on() local
87 dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_on()
94 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_power_off() local
96 writel(0, dphy->regs + DPHY_CMN_SSM); in cdns_dphy_rx_power_off()
128 static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, in cdns_dphy_rx_wait_lane_ready() argument
135 void __iomem *reg = dphy->regs; in cdns_dphy_rx_wait_lane_ready()
171 struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); in cdns_dphy_rx_configure() local
182 writel(reg, dphy->regs + DPHY_LANE); in cdns_dphy_rx_configure()
195 writel(reg, dphy->regs + DPHY_BAND_CFG); in cdns_dphy_rx_configure()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 18 #include <linux/phy/phy-mipi-dphy.h>
183 void (*tx_power_on)(struct sun6i_dphy *dphy);
202 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
204 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
205 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
206 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
213 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
220 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
225 static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) in sun6i_a31_mipi_dphy_tx_power_on() argument
227 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_a31_mipi_dphy_tx_power_on()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/starfive/ |
| D | phy-jh7110-dphy-rx.c | 3 * StarFive JH7110 DPHY RX driver
80 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
81 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
93 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
98 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192)); in stf_dphy_configure()
104 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196)); in stf_dphy_configure()
107 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200)); in stf_dphy_configure()
114 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_power_on() local
117 ret = pm_runtime_resume_and_get(dphy->dev); in stf_dphy_power_on()
121 ret = regulator_enable(dphy->mipi_0p9); in stf_dphy_power_on()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 18 #include <linux/phy/phy-mipi-dphy.h>
99 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
101 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
102 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
103 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
110 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
117 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
124 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_power_on() local
125 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_dphy_power_on()
127 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_power_on()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ |
| D | sun8i_a83t_dphy.c | 13 static int sun8i_a83t_dphy_configure(struct phy *dphy, in sun8i_a83t_dphy_configure() argument
19 static int sun8i_a83t_dphy_power_on(struct phy *dphy) in sun8i_a83t_dphy_power_on() argument
21 struct sun8i_a83t_mipi_csi2_device *csi2_dev = phy_get_drvdata(dphy); in sun8i_a83t_dphy_power_on()
36 static int sun8i_a83t_dphy_power_off(struct phy *dphy) in sun8i_a83t_dphy_power_off() argument
38 struct sun8i_a83t_mipi_csi2_device *csi2_dev = phy_get_drvdata(dphy); in sun8i_a83t_dphy_power_off()
57 csi2_dev->dphy = devm_phy_create(dev, NULL, &sun8i_a83t_dphy_ops); in sun8i_a83t_dphy_register()
58 if (IS_ERR(csi2_dev->dphy)) { in sun8i_a83t_dphy_register()
60 return PTR_ERR(csi2_dev->dphy); in sun8i_a83t_dphy_register()
63 phy_set_drvdata(csi2_dev->dphy, csi2_dev); in sun8i_a83t_dphy_register()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | cdns,dphy.txt | 1 Cadence DPHY
4 Cadence DPHY block.
7 - compatible: should be set to "cdns,dphy".
8 - reg: physical base address and length of the DPHY registers.
9 - clocks: DPHY reference clocks.
14 dphy0: dphy@fd0e0000{
15 compatible = "cdns,dphy";
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| D | rockchip-mipi-dphy-rx0.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
19 const: rockchip,rk3399-mipi-dphy-rx0
29 - const: dphy-ref
30 - const: dphy-cfg
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
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| D | rockchip,px30-dsi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
61 compatible = "rockchip,px30-dsi-dphy";
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| D | mixel,mipi-dsi-phy.txt | 9 - "fsl,imx8mq-mipi-dphy"
12 - "phy_ref": phandle and specifier referring to the DPHY ref clock
22 dphy: dphy@30a0030 {
23 compatible = "fsl,imx8mq-mipi-dphy";
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| D | allwinner,sun6i-a31-mipi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
19 - const: allwinner,sun6i-a31-mipi-dphy
21 - const: allwinner,sun50i-a64-mipi-dphy
22 - const: allwinner,sun6i-a31-mipi-dphy
53 compatible = "allwinner,sun6i-a31-mipi-dphy";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | rockchip,px30-dsi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
22 - rockchip,rv1126-dsi-dphy
63 compatible = "rockchip,px30-dsi-dphy";
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| D | allwinner,sun6i-a31-mipi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
22 - const: allwinner,sun50i-a64-mipi-dphy
23 - const: allwinner,sun6i-a31-mipi-dphy
25 - const: allwinner,sun20i-d1-mipi-dphy
26 - const: allwinner,sun50i-a100-mipi-dphy
75 compatible = "allwinner,sun6i-a31-mipi-dphy";
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| D | rockchip-mipi-dphy-rx0.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
19 const: rockchip,rk3399-mipi-dphy-rx0
29 - const: dphy-ref
30 - const: dphy-cfg
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
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| D | rockchip-inno-csi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
22 - rockchip,rk3368-csi-dphy
23 - rockchip,rk3568-csi-dphy
71 compatible = "rockchip,px30-csi-dphy";
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| D | mixel,mipi-dsi-phy.yaml | 23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
59 const: fsl,imx8mq-mipi-dphy
73 const: fsl,imx8qxp-mipi-dphy
88 dphy: dphy@30a0030 {
89 compatible = "fsl,imx8mq-mipi-dphy";
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| D | cdns,dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
7 title: Cadence DPHY
15 - cdns,dphy
16 - ti,j721e-dphy
51 compatible = "cdns,dphy";
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| D | cdns,dphy-rx.yaml | 4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
7 title: Cadence DPHY Rx
15 - const: cdns,dphy-rx
38 compatible = "cdns,dphy-rx";
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| /kernel/linux/linux-5.10/drivers/media/platform/marvell-ccic/ |
| D | mmp-driver.c | 51 * calc the dphy register values
52 * There are three dphy registers being used.
53 * dphy[0] - CSI2_DPHY3
54 * dphy[1] - CSI2_DPHY5
55 * dphy[2] - CSI2_DPHY6
73 * dphy[0] - CSI2_DPHY3: in mmpcam_calc_dphy()
75 * defines the time that the DPHY in mmpcam_calc_dphy()
99 pdata->dphy[0] = in mmpcam_calc_dphy()
107 pdata->dphy[0] = in mmpcam_calc_dphy()
129 * dphy[2] - CSI2_DPHY6: in mmpcam_calc_dphy()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/marvell/ |
| D | mmp-driver.c | 51 * calc the dphy register values
52 * There are three dphy registers being used.
53 * dphy[0] - CSI2_DPHY3
54 * dphy[1] - CSI2_DPHY5
55 * dphy[2] - CSI2_DPHY6
73 * dphy[0] - CSI2_DPHY3: in mmpcam_calc_dphy()
75 * defines the time that the DPHY in mmpcam_calc_dphy()
99 pdata->dphy[0] = in mmpcam_calc_dphy()
107 pdata->dphy[0] = in mmpcam_calc_dphy()
129 * dphy[2] - CSI2_DPHY6: in mmpcam_calc_dphy()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/kmb/ |
| D | kmb_regs.h | 647 #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \ argument
649 ((dphy) + (offset)))
650 #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ argument
652 ((dphy) + (offset)))
659 #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ argument
661 + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val)
667 #define GET_STOPSTATE_DATA(dev, dphy) \ argument
669 ((dphy) / 4) * 4)) >> \
670 (((dphy % 4) * 8) + 4)) & 0x03)
675 #define SET_DPHY_TEST_CTRL0(dev, dphy) \ argument
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 81 struct phy *dphy; member
119 ret = phy_power_on(csi2rx->dphy); in csi2rx_configure_ext_dphy()
123 ret = phy_configure(csi2rx->dphy, &opts); in csi2rx_configure_ext_dphy()
125 phy_power_off(csi2rx->dphy); in csi2rx_configure_ext_dphy()
167 /* Enable DPHY clk and data lanes. */ in csi2rx_start()
168 if (csi2rx->dphy) { in csi2rx_start()
180 "Failed to configure external DPHY: %d\n", ret); in csi2rx_start()
235 if (csi2rx->dphy) { in csi2rx_start()
237 phy_power_off(csi2rx->dphy); in csi2rx_start()
266 if (csi2rx->dphy) { in csi2rx_stop()
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/rockchip/rkisp1/ |
| D | rkisp1-csi.c | 16 #include <linux/phy/phy-mipi-dphy.h>
186 phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY); in rkisp1_csi_start()
187 phy_configure(csi->dphy, &opts); in rkisp1_csi_start()
188 phy_power_on(csi->dphy); in rkisp1_csi_start()
205 phy_power_off(csi->dphy); in rkisp1_csi_stop()
224 * Disable DPHY errctrl interrupt, because this dphy in rkisp1_csi_isr()
237 * Enable DPHY errctrl interrupt again, if mipi have receive in rkisp1_csi_isr()
242 * Enable DPHY errctrl interrupt again, if mipi have receive in rkisp1_csi_isr()
541 csi->dphy = devm_phy_get(rkisp1->dev, "dphy"); in rkisp1_csi_init()
542 if (IS_ERR(csi->dphy)) in rkisp1_csi_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/amlogic/ |
| D | Kconfig | 41 tristate "Meson G12A MIPI Analog DPHY driver"
48 Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
98 tristate "Meson AXG MIPI DPHY driver"
105 Enable this to support the Meson MIPI DPHY found in Meson AXG
|