| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
23 "BriefDescription": "Memory controller clock ticks",
30 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
50 "BriefDescription": "Pre-charges due to page misses",
59 "BriefDescription": "Pre-charge for reads",
68 "BriefDescription": "Pre-charge for writes",
77 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
82 …DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Control…
87 "BriefDescription": "All DRAM CAS Commands issued",
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 1 * Rockchip rk3399 DMC (Dynamic Memory Controller) device
4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
17 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
23 "BriefDescription": "DRAM Activate Count : All Activates",
27 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha…
32 "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
36 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on…
41 "BriefDescription": "All DRAM CAS commands issued",
45 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
23 "BriefDescription": "Memory controller clock ticks",
30 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
50 "BriefDescription": "Pre-charges due to page misses",
59 "BriefDescription": "Pre-charge for reads",
68 "BriefDescription": "Pre-charge for writes",
98 "ScaleUnit": "6.103515625E-5MB",
107 "ScaleUnit": "6.103515625E-5MB",
118 "ScaleUnit": "6.103515625E-5MB",
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/sunxi/ |
| D | allwinner,sun4i-a10-mbus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Memory Bus (MBUS) controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The MBUS controller drives the MBUS that other devices in the SoC
20 the interconnects and interconnect-names properties set to the MBUS
21 controller and with "dma-mem" as the interconnect name.
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | uncore-memory.json | 3 "BriefDescription": "DRAM Activate Count : All Activates",
7 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha…
12 "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
16 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on…
21 "BriefDescription": "All DRAM CAS commands issued",
25 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
30 "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
34 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
39 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
43 …ption": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_C…
[all …]
|
| D | other.json | 3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
6 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX…
14 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct…
22 … running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). …
92 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
94 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
101 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
110 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys…
128 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
130 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
[all …]
|
| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
7 This driver supports the Memory Controller (MC) hardware found on
11 bool "NVIDIA Tegra20 External Memory Controller driver"
15 This driver is for the External Memory Controller (EMC) found on
16 Tegra20 chips. The EMC controls the external DRAM on the board.
21 bool "NVIDIA Tegra30 External Memory Controller driver"
25 This driver is for the External Memory Controller (EMC) found on
26 Tegra30 chips. The EMC controls the external DRAM on the board.
31 bool "NVIDIA Tegra124 External Memory Controller driver"
[all …]
|
| /kernel/linux/linux-6.6/drivers/memory/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
8 This driver supports the Memory Controller (MC) hardware found on
14 tristate "NVIDIA Tegra20 External Memory Controller driver"
21 This driver is for the External Memory Controller (EMC) found on
22 Tegra20 chips. The EMC controls the external DRAM on the board.
27 tristate "NVIDIA Tegra30 External Memory Controller driver"
33 This driver is for the External Memory Controller (EMC) found on
34 Tegra30 chips. The EMC controls the external DRAM on the board.
39 tristate "NVIDIA Tegra124 External Memory Controller driver"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | uncore-memory.json | 3 "BriefDescription": "DRAM Activate Count",
7 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued…
11 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
19 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
27 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
35 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
43 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
51 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read…
59 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Writ…
70 "PublicDescription": "Uncore Fixed Counter - uclks",
[all …]
|
| /kernel/linux/linux-5.10/drivers/edac/ |
| D | i3000_edac.c | 2 * Intel 3000/3010 Memory Controller kernel module
5 * Intel D82875P Memory Controller kernel module
25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
31 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
54 deap |= (edeap & 1) << (32 - PAGE_SHIFT); in deap_pfn()
60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; in deap_offset()
68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
70 * 7:0 DRAM ECC Syndrome
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
[all …]
|
| D | ie31200_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
9 * Since the DRAM controller is on the cpu chip, we can use its PCI device
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
[all …]
|
| D | amd64_edac.h | 2 * AMD64 class Memory Controller kernel module
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
76 * memory controller for the node that the DramAddr is associated
77 * with. The memory controller then maps the InputAddr to a csrow.
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
105 * PCI-defined configuration space registers
[all …]
|
| D | altera_edac.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
10 #include <linux/arm-smccc.h>
14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
[all …]
|
| D | i82975x_edac.c | 2 * Intel 82975X Memory Controller kernel module
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
37 * 31:7 128 byte cache-line address
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 * 7:0 DRAM ECC Syndrome
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
[all …]
|
| /kernel/linux/linux-6.6/drivers/edac/ |
| D | i3000_edac.c | 2 * Intel 3000/3010 Memory Controller kernel module
5 * Intel D82875P Memory Controller kernel module
25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
31 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
54 deap |= (edeap & 1) << (32 - PAGE_SHIFT); in deap_pfn()
60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; in deap_offset()
68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
70 * 7:0 DRAM ECC Syndrome
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
[all …]
|
| D | ie31200_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
9 * Since the DRAM controller is on the cpu chip, we can use its PCI device
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
[all …]
|
| D | amd64_edac.h | 2 * AMD64 class Memory Controller kernel module
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
57 * is within a range affected by memory hoisting. The DRAM Base
58 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
61 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
77 * memory controller for the node that the DramAddr is associated
78 * with. The memory controller then maps the InputAddr to a csrow.
84 * The memory controller for a given node uses its DRAM CS Base and
85 * DRAM CS Mask registers to map an InputAddr to a csrow. See
105 * PCI-defined configuration space registers
[all …]
|
| D | altera_edac.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
10 #include <linux/arm-smccc.h>
14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
[all …]
|
| D | i82975x_edac.c | 2 * Intel 82975X Memory Controller kernel module
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
37 * 31:7 128 byte cache-line address
42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 * 7:0 DRAM ECC Syndrome
47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
61 * 1 ECC UE (multibit DRAM error)
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | other.json | 26 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
28 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
35 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
44 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys…
62 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
64 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
71 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
98 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke…
116 …d data reads that were supplied by DRAM on a distant memory controller of this socket when the sys…
134 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
[all …]
|
| D | uncore-memory.json | 3 "BriefDescription": "Cycles - at UCLK",
186 "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
195 "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
204 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
213 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
286 "BriefDescription": "Multi-socket cacheline Directory update from A to I",
294 "BriefDescription": "Multi-socket cacheline Directory update from A to S",
302 "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
310 "BriefDescription": "Multi-socket cacheline Directory Updates",
321 "BriefDescription": "Multi-socket cacheline Directory Updates",
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/host/ |
| D | xhci-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Gregory CLEMENT <gregory.clement@free-electrons.com>
16 #include "xhci-mvebu.h"
24 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
34 /* Program each DRAM CS in a seperate window */ in xhci_mvebu_mbus_config()
35 for (win = 0; win < dram->num_cs; win++) { in xhci_mvebu_mbus_config()
36 const struct mbus_dram_window *cs = &dram->cs[win]; in xhci_mvebu_mbus_config()
38 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in xhci_mvebu_mbus_config()
39 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
42 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config()
[all …]
|
| D | ehci-orion.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/usb/host/ehci-orion.c
13 #include <linux/platform_data/usb-ehci-orion.h>
21 #include <linux/dma-mapping.h>
25 #define rdl(off) readl_relaxed(hcd->regs + (off))
26 #define wrl(off, val) writel_relaxed((val), hcd->regs + (off))
61 #define hcd_to_orion_priv(h) ((struct orion_ehci_hcd *)hcd_to_ehci(h)->priv)
68 static const char hcd_name[] = "ehci-orion";
73 * Implement Orion USB controller specification guidelines
85 * Reset controller in orion_usb_phy_v1_setup()
[all …]
|