| /kernel/linux/linux-6.6/drivers/pmdomain/qcom/ |
| D | cpr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
26 #include <linux/nvmem-consumer.h>
28 /* Register Offsets for RB-CPR and Bit Definitions */
99 #define RBCPR_RESULT0_STEP_UP_SHIFT 1
107 #define CPR_INT_MIN BIT(1)
124 #define FUSE_REVISION_UNKNOWN (-1)
251 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
253 return !drv->loop_disabled; in cpr_is_allowed()
256 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
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| /kernel/linux/linux-5.10/drivers/soc/qcom/ |
| D | cpr.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
100 #define RBCPR_RESULT0_STEP_UP_SHIFT 1
108 #define CPR_INT_MIN BIT(1)
125 #define FUSE_REVISION_UNKNOWN (-1)
252 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
254 return !drv->loop_disabled; in cpr_is_allowed()
257 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
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| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | cpuidle-qcom-spm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
22 #include <asm/proc-fns.h>
105 .pmic_data[1] = 0x00A4001C,
112 static inline void spm_register_write(struct spm_driver_data *drv, in spm_register_write() argument
115 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
116 writel_relaxed(val, drv->reg_base + in spm_register_write()
117 drv->reg_data->reg_offset[reg]); in spm_register_write()
121 static inline void spm_register_write_sync(struct spm_driver_data *drv, in spm_register_write_sync() argument
126 if (!drv->reg_data->reg_offset[reg]) in spm_register_write_sync()
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| D | driver.c | 2 * driver.c - driver support
4 * (C) 2006-2007 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
29 * __cpuidle_get_cpu_driver - return the cpuidle driver tied to a CPU.
41 * __cpuidle_unset_driver - unset per CPU driver variables.
42 * @drv: a valid pointer to a struct cpuidle_driver
45 * variable. If @drv is different from the registered driver, the corresponding
48 static inline void __cpuidle_unset_driver(struct cpuidle_driver *drv) in __cpuidle_unset_driver() argument
52 for_each_cpu(cpu, drv->cpumask) { in __cpuidle_unset_driver()
54 if (drv != __cpuidle_get_cpu_driver(cpu)) in __cpuidle_unset_driver()
62 * __cpuidle_set_driver - set per CPU driver variables for the given driver.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
63 struct mac_driver *drv = (struct mac_driver *)mac_drv; in hns_gmac_enable() local
67 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1); in hns_gmac_enable()
71 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0); in hns_gmac_enable()
72 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1); in hns_gmac_enable()
78 struct mac_driver *drv = (struct mac_driver *)mac_drv; in hns_gmac_disable() local
82 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0); in hns_gmac_disable()
86 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1); in hns_gmac_disable()
87 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0); in hns_gmac_disable()
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| D | hns_dsaf_xgmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
6 #include <linux/io-64-nonatomic-hi-lo.h>
87 *hns_xgmac_tx_enable - xgmac port tx enable
88 *@drv: mac driver
91 static void hns_xgmac_tx_enable(struct mac_driver *drv, u32 value) in hns_xgmac_tx_enable() argument
93 dsaf_set_dev_bit(drv, XGMAC_MAC_ENABLE_REG, XGMAC_ENABLE_TX_B, !!value); in hns_xgmac_tx_enable()
97 *hns_xgmac_rx_enable - xgmac port rx enable
98 *@drv: mac driver
101 static void hns_xgmac_rx_enable(struct mac_driver *drv, u32 value) in hns_xgmac_rx_enable() argument
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| /kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
63 struct mac_driver *drv = (struct mac_driver *)mac_drv; in hns_gmac_enable() local
67 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1); in hns_gmac_enable()
71 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0); in hns_gmac_enable()
72 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1); in hns_gmac_enable()
78 struct mac_driver *drv = (struct mac_driver *)mac_drv; in hns_gmac_disable() local
82 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0); in hns_gmac_disable()
86 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1); in hns_gmac_disable()
87 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0); in hns_gmac_disable()
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| D | hns_dsaf_xgmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
6 #include <linux/io-64-nonatomic-hi-lo.h>
87 *hns_xgmac_tx_enable - xgmac port tx enable
88 *@drv: mac driver
91 static void hns_xgmac_tx_enable(struct mac_driver *drv, u32 value) in hns_xgmac_tx_enable() argument
93 dsaf_set_dev_bit(drv, XGMAC_MAC_ENABLE_REG, XGMAC_ENABLE_TX_B, !!value); in hns_xgmac_tx_enable()
97 *hns_xgmac_rx_enable - xgmac port rx enable
98 *@drv: mac driver
101 static void hns_xgmac_rx_enable(struct mac_driver *drv, u32 value) in hns_xgmac_rx_enable() argument
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| /kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-drv.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
8 #include <linux/dma-mapping.h>
13 #include "iwl-drv.h"
14 #include "iwl-csr.h"
15 #include "iwl-debug.h"
16 #include "iwl-trans.h"
17 #include "iwl-op-mode.h"
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | mena21_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
42 static unsigned int a21_wdt_get_bootstatus(struct a21_wdt_drv *drv) in a21_wdt_get_bootstatus() argument
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
55 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_start() local
57 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1); in a21_wdt_start()
64 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_stop() local
66 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0); in a21_wdt_stop()
73 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_ping() local
[all …]
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| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | mena21_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
42 static unsigned int a21_wdt_get_bootstatus(struct a21_wdt_drv *drv) in a21_wdt_get_bootstatus() argument
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
55 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_start() local
57 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1); in a21_wdt_start()
64 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_stop() local
66 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0); in a21_wdt_stop()
73 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_ping() local
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/ |
| D | iwl-drv.c | 8 * Copyright(c) 2007 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.
31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
32 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
63 #include <linux/dma-mapping.h>
68 #include "iwl-drv.h"
69 #include "iwl-csr.h"
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| /kernel/linux/linux-6.6/drivers/soc/qcom/ |
| D | spm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
124 .pmic_data[1] = 0x00030000,
134 .pmic_data[1] = 0x00030000,
185 .pmic_data[1] = 0x00A4001C,
192 static inline void spm_register_write(struct spm_driver_data *drv, in spm_register_write() argument
195 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
196 writel_relaxed(val, drv->reg_base + in spm_register_write()
197 drv->reg_data->reg_offset[reg]); in spm_register_write()
201 static inline void spm_register_write_sync(struct spm_driver_data *drv, in spm_register_write_sync() argument
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | s5pv210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/pinctrl/samsung.h>
24 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
25 samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
30 gpio-controller;
31 #gpio-cells = <2>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
38 gpio-controller;
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| D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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| D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
14 #include <dt-bindings/pinctrl/samsung.h>
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
22 #interrupt-cells = <2>;
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| D | exynos4412-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
23 gpio-controller;
24 #gpio-cells = <2>;
26 interrupt-controller;
27 #interrupt-cells = <2>;
[all …]
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| D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/ |
| D | exynos4x12-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
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| D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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| D | s5pv210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
26 gpio-controller;
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| D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
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| D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rockchip-pinconf.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | qcom-cpufreq-nvmem.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * defines the voltage and frequency value based on the msm-id in SMEM
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
15 * operating-points-v2 table when it is parsed by the OPP framework.
23 #include <linux/nvmem-consumer.h>
53 struct qcom_cpufreq_drv *drv);
110 case 1: in get_krait_bin_format_b()
119 /* 4 bits of PVS are in efuse register bits 31, 8-6. */ in get_krait_bin_format_b()
133 pte_efuse = *(((u32 *)buf) + 1); in get_krait_bin_format_b()
155 /* The first 4 bytes are format, next to them is the actual msm-id */ in qcom_cpufreq_get_msm_id()
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