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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
[all …]
Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
[all …]
Dqcom,sdm845-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
[all …]
Dqcom,msm8998-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,msm8998-mdss
25 - description: Display AHB clock
26 - description: Display AXI clock
[all …]
Dqcom,sm8550-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8550-mdss
24 - description: Display MDSS AHB
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/panel/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
46 as found in the YLM RS-97 handheld gaming console.
49 tristate "Boe BF060Y8M-AJ0 panel"
54 Say Y here if you want to enable support for Boe BF060Y8M-AJ0
56 uses 24 bit RGB per pixel. It provides a MIPI DSI interface to
57 the host and backlight is controlled through DSI commands.
66 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
67 24 bit RGB per pixel. It provides a MIPI DSI interface to
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/panel/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
39 24 bit RGB per pixel. It provides a MIPI DSI interface to
40 the host and has a built-in LED backlight.
49 45NA WUXGA PANEL DSI Video Mode panel
57 This driver supports LVDS panels that don't require device-specific
59 backlight handling if the panel is attached to a backlight controller.
79 KD35T133 controller for 320x480 LCD panels with MIPI-DSI
89 4-lane 800x1280 MIPI DSI panel.
92 tristate "Feiyang FY07024DI26A30-D MIPI-DSI LCD panel"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@st.com>
11 - Yannick Fertre <yannick.fertre@st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
26 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
28 It has a flexible configuration of MIPI DSI signal input
50 ChromeOS EC ANX7688 is an ultra-low power
51 4K Ultra-HD (4096x2160p60) mobile HD transmitter
53 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
54 to the ChromeOS Embedded Controller.
60 Driver for display connectors with support for DDC and hot-plug
64 on ARM-based platforms. Saying Y here when this driver is not needed
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
13 - Xinlei Lee <xinlei.lee@mediatek.com>
16 The MediaTek DSI function block is a sink of the display subsystem and can
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
21 - enum:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
[all …]
Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
[all …]
Damlogic,meson-g12a-dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 - A Synopsys DesignWare MIPI DSI Host Controller IP
16 - A TOP control block controlling the Clocks & Resets of the IP
19 - $ref: dsi-controller.yaml#
24 - amlogic,meson-g12a-dw-mipi-dsi
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/hisilicon/
Ddw-dsi.txt1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
21 dsi: dsi@f4107800 {
22 compatible = "hisilicon,hi6220-dsi";
25 clock-names = "pclk";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/hisilicon/
Ddw-dsi.txt1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
21 dsi: dsi@f4107800 {
22 compatible = "hisilicon,hi6220-dsi";
25 clock-names = "pclk";
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "Cadence DPI/DSI bridge"
27 Support Cadence DPI to DSI bridge. This is an internal
44 Driver for display connectors with support for DDC and hot-plug
45 detection. Most display controller handle display connectors
48 on ARM-based platforms. Saying Y here when this driver is not needed
52 tristate "Lontium LT9611 DSI/HDMI bridge"
60 Driver for Lontium LT9611 DSI to HDMI bridge
61 chip driver that converts dual DSI and I2S to
75 tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw"
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
66 the MSM DRM driver. It is the older display controller found in
76 the MSM DRM driver. It is the display controller found in devices
86 the MSM DRM driver. It is the display controller found in devices
100 bool "Enable DSI support in MSM DRM driver"
106 Choose this option if you have a need for MIPI DSI connector
110 bool "Enable DSI 28nm PHY driver in MSM DRM"
114 Choose this option if the 28nm DSI PHY is used on the platform.
117 bool "Enable DSI 20nm PHY driver in MSM DRM"
121 Choose this option if the 20nm DSI PHY is used on the platform.
[all …]
DNOTES4 display controller blocks at play:
5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
9 (I don't have a completely clear picture on which display controller
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
19 display controller blocks. And I for sure don't want to have to deal
20 with N different kms devices from xf86-video-freedreno. Plus, it
26 'struct msm_kms' implementations, depending on display controller.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.txt1 Mediatek DSI Device
4 The Mediatek DSI function block is a sink of the display subsystem and can
5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
DNOTES4 display controller blocks at play:
5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
9 (I don't have a completely clear picture on which display controller
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
19 display controller blocks. And I for sure don't want to have to deal
20 with N different kms devices from xf86-video-freedreno. Plus, it
26 'struct msm_kms' implementations, depending on display controller.
[all …]

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