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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-7nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 7nm PHY
10 - Jonathan Marek <jonathan@marek.ca>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-7nm
19 - qcom,dsi-phy-7nm-8150
20 - qcom,sc7280-dsi-phy-7nm
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Ddsi-phy-10nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 10nm PHY
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
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Dqcom,sdm845-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
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Dqcom,msm8998-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,msm8998-mdss
25 - description: Display AHB clock
26 - description: Display AXI clock
[all …]
Dqcom,sm6350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
24 - description: Display AHB clock from gcc
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Dqcom,sc7180-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7180-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
71 bool "Enable DSI support in MSM DRM driver"
77 Choose this option if you have a need for MIPI DSI connector
81 bool "Enable DSI PLL driver in MSM DRM"
85 Choose this option to enable DSI PLL driver which provides DSI
89 bool "Enable DSI 28nm PHY driver in MSM DRM"
93 Choose this option if the 28nm DSI PHY is used on the platform.
96 bool "Enable DSI 20nm PHY driver in MSM DRM"
100 Choose this option if the 20nm DSI PHY is used on the platform.
103 bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
100 bool "Enable DSI support in MSM DRM driver"
106 Choose this option if you have a need for MIPI DSI connector
110 bool "Enable DSI 28nm PHY driver in MSM DRM"
114 Choose this option if the 28nm DSI PHY is used on the platform.
117 bool "Enable DSI 20nm PHY driver in MSM DRM"
121 Choose this option if the 20nm DSI PHY is used on the platform.
124 bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
128 Choose this option if the 28nm DSI PHY 8960 variant is used on the
132 bool "Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)"
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
47 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
[all …]
Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
[all …]
Ddsi_phy_28nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
10 #include "dsi.xml.h"
14 * DSI PLL 28nm - clock diagram (eg: DSI0):
19 * +------+ | +----+ | |\ dsi0byte_mux
20 * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ |
21 * | +------+ +----+ | m| | +----+
22 * | | u|--o--| /4 |-- dsi0pllbyte
23 * | | x| +----+
24 * o--------------------------| /
[all …]
Ddsi_phy_28nm_8960.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
10 #include "dsi.xml.h"
14 * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1):
17 * +------+
18 * dsi1vco_clk ----o-----| DIV1 |---dsi1pllbit (not exposed as clock)
19 * F * byte_clk | +------+
22 * | +------+
23 * o-----| DIV2 |---dsi0pllbyte---o---> To byte RCG
[all …]
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
51 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc()
52 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc()
[all …]
Ddsi_phy.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include "dsi.h"
16 /* v3.0.0 10nm implementation that requires the old timings settings */
20 int (*init) (struct msm_dsi_phy *phy);
21 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
23 void (*disable)(struct msm_dsi_phy *phy);
33 * if the source PLL selection bit should be set for each PHY.
69 /* For PHY v2 only */
97 * PHY internal functions
107 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
15 #include <linux/phy/phy.h>
40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
177 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) argument
230 /* dual-channel */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_28nm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
10 #include "dsi.xml.h"
13 * DSI PLL 28nm - clock diagram (eg: DSI0):
18 * +------+ | +----+ | |\ dsi0byte_mux
19 * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ |
20 * | +------+ +----+ | m| | +----+
21 * | | u|--o--| /4 |-- dsi0pllbyte
22 * | | x| +----+
[all …]
Ddsi_pll_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
14 * DSI PLL 10nm - clock diagram (eg: DSI0):
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
[all …]
Ddsi_pll_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
10 #include "dsi.xml.h"
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
Dqcom-msm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
17 #address-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dmsm8953.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
[all …]
Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]

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