| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "dsi.h"
22 struct msm_dsi *dsi[DSI_MAX]; member
37 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
42 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
49 /* We assume 2 dsi nodes have the same information of dual-dsi and in dsi_mgr_parse_dual_dsi()
50 * sync-mode, and only one node specifies master in case of dual mode. in dsi_mgr_parse_dual_dsi()
52 if (!msm_dsim->is_dual_dsi) in dsi_mgr_parse_dual_dsi()
53 msm_dsim->is_dual_dsi = of_property_read_bool( in dsi_mgr_parse_dual_dsi()
54 np, "qcom,dual-dsi-mode"); in dsi_mgr_parse_dual_dsi()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/ |
| D | truly,nt35597.txt | 1 Truly model NT35597 DSI display driver
7 - compatible: should be "truly,nt35597-2K-display"
8 - vdda-supply: phandle of the regulator that provides the supply voltage
10 - vdispp-supply: phandle of the regulator that provides the supply voltage
12 - vdispn-supply: phandle of the regulator that provides the supply voltage
14 - reset-gpios: phandle of gpio for reset line
15 This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
17 - mode-gpios: phandle of the gpio for choosing the mode of the display
18 for single DSI or Dual DSI
19 This should be low for dual DSI and high for single DSI mode
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | truly,nt35597.txt | 1 Truly model NT35597 DSI display driver
7 - compatible: should be "truly,nt35597-2K-display"
8 - vdda-supply: phandle of the regulator that provides the supply voltage
10 - vdispp-supply: phandle of the regulator that provides the supply voltage
12 - vdispn-supply: phandle of the regulator that provides the supply voltage
14 - reset-gpios: phandle of gpio for reset line
15 This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
17 - mode-gpios: phandle of the gpio for choosing the mode of the display
18 for single DSI or Dual DSI
19 This should be low for dual DSI and high for single DSI mode
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/ |
| D | dsi-controller-main.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
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| /kernel/linux/linux-5.10/drivers/gpu/drm/panel/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
28 NT35596 1080x1920 video mode panel as found in some Asus
38 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
39 24 bit RGB per pixel. It provides a MIPI DSI interface to
40 the host and has a built-in LED backlight.
49 45NA WUXGA PANEL DSI Video Mode panel
57 This driver supports LVDS panels that don't require device-specific
79 KD35T133 controller for 320x480 LCD panels with MIPI-DSI
89 4-lane 800x1280 MIPI DSI panel.
92 tristate "Feiyang FY07024DI26A30-D MIPI-DSI LCD panel"
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/ |
| D | ti-sn65dsi83.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
[all …]
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| D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0
39 /* DSI layer registers */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
49 #define LCDCTRL_EVTMODE BIT(5) /* Event mode */
50 #define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */
66 /* Lane enable PPI and DSI register bits */
77 struct drm_display_mode mode; member
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write() local
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| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
48 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
50 /* DSI PPI Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
89 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/panel/ |
| D | sharp,lq101r1sx01.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/panel/ |
| D | sharp,lq101r1sx01.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "dsi.h"
24 struct msm_dsi *dsi[DSI_MAX]; member
39 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
44 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
51 /* We assume 2 dsi nodes have the same information of bonded dsi and in dsi_mgr_parse_of()
52 * sync-mode, and only one node specifies master in case of bonded mode. in dsi_mgr_parse_of()
54 if (!msm_dsim->is_bonded_dsi) in dsi_mgr_parse_of()
55 msm_dsim->is_bonded_dsi = of_property_read_bool(np, "qcom,dual-dsi-mode"); in dsi_mgr_parse_of()
57 if (msm_dsim->is_bonded_dsi) { in dsi_mgr_parse_of()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/panel/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
37 NT35596 1080x1920 video mode panel as found in some Asus
46 as found in the YLM RS-97 handheld gaming console.
49 tristate "Boe BF060Y8M-AJ0 panel"
54 Say Y here if you want to enable support for Boe BF060Y8M-AJ0
56 uses 24 bit RGB per pixel. It provides a MIPI DSI interface to
57 the host and backlight is controlled through DSI commands.
66 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dsi_vbt.c | 34 #include <asm/intel-mid.h>
112 /* ICL DSI Display GPIO Pins */
128 * If single link DSI is being used on any port, the VBT sequence block in intel_dsi_seq_port_to_port()
132 if (hweight8(intel_dsi->ports) == 1) in intel_dsi_seq_port_to_port()
133 return ffs(intel_dsi->ports) - 1; in intel_dsi_seq_port_to_port()
136 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
138 else if (intel_dsi->ports & BIT(PORT_C)) in intel_dsi_seq_port_to_port()
148 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in mipi_exec_send_packet()
154 drm_dbg_kms(&dev_priv->drm, "\n"); in mipi_exec_send_packet()
166 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])) in mipi_exec_send_packet()
[all …]
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| D | intel_dsi.h | 35 /* Dual Link support */
54 /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
56 u16 ports; /* VLV DSI */
57 u16 phys; /* ICL DSI */
60 /* if true, use HS mode, otherwise LP */
66 /* Video mode or command mode */
69 /* number of DSI lanes */
76 * video mode pixel format
82 /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
150 return container_of(&encoder->base, struct intel_dsi, base.base); in enc_to_intel_dsi()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_dsi_vbt.c | 119 /* ICL DSI Display GPIO Pins */
135 * If single link DSI is being used on any port, the VBT sequence block in intel_dsi_seq_port_to_port()
139 if (hweight8(intel_dsi->ports) == 1) in intel_dsi_seq_port_to_port()
140 return ffs(intel_dsi->ports) - 1; in intel_dsi_seq_port_to_port()
143 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
145 else if (intel_dsi->ports & BIT(PORT_C)) in intel_dsi_seq_port_to_port()
155 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in mipi_exec_send_packet()
161 drm_dbg_kms(&dev_priv->drm, "\n"); in mipi_exec_send_packet()
173 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])) in mipi_exec_send_packet()
176 dsi_device = intel_dsi->dsi_hosts[port]->device; in mipi_exec_send_packet()
[all …]
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| D | intel_dsi.h | 35 /* Dual Link support */
54 /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
56 u16 ports; /* VLV DSI */
57 u16 phys; /* ICL DSI */
60 /* if true, use HS mode, otherwise LP */
66 /* Video mode or command mode */
69 /* number of DSI lanes */
76 * video mode pixel format
148 return container_of(&encoder->base, struct intel_dsi, base.base); in enc_to_intel_dsi()
153 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; in is_vid_mode()
[all …]
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| D | icl_dsi.c | 71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
102 struct mipi_dsi_device *dsi; in wait_for_cmds_dispatched_to_panel() local
108 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
115 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
118 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
119 ret = mipi_dsi_dcs_nop(dsi); in wait_for_cmds_dispatched_to_panel()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/ |
| D | dw-mipi-dsi-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
230 /* dual-channel */
306 return -EINVAL; in max_mbps_to_parameter()
309 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
226 #define VPG_DEFS(name, dsi) \ argument
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \ argument
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi; member
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 This driver provides kernel mode setting and buffer
67 bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
71 for the Synopsys DesignWare dsi driver. If you want to
72 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
89 support LVDS, rgb, dual LVDS output mode. say Y to enable its
|
| D | dw-mipi-dsi-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
264 /* dual-channel */
355 return -EINVAL; in max_mbps_to_parameter()
358 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
226 #define VPG_DEFS(name, dsi) \ argument
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \ argument
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi; member
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
35 /* DSI D-PHY Layer Registers */
48 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
50 /* DSI PPI Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
89 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
97 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | stm32f469-disco.dts | 2 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
22 * MA 02110-1301 USA
48 /dts-v1/;
50 #include "stm32f469-pinctrl.dtsi"
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
55 model = "STMicroelectronics STM32F469i-DISCO board";
56 compatible = "st,stm32f469i-disco", "st,stm32f469";
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