| /kernel/linux/linux-6.6/drivers/pwm/ |
| D | pwm-ntxec.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * e-book readers designed by the original design manufacturer Netronix, Inc.
13 * - The get_state callback is not implemented, because the current state of
15 * - The hardware can only generate normal polarity output.
16 * - The period and duty cycle can't be changed together in one atomic action.
45 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
58 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
63 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
66 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
69 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
[all …]
|
| D | pwm-cros-ec.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/mfd/cros_ec.h>
19 * struct cros_ec_pwm_device - Driver data for EC PWM
34 * struct cros_ec_pwm - per-PWM driver data
35 * @duty_cycle: cached duty cycle
52 return -ENOMEM; in cros_ec_pwm_request()
76 return -EINVAL; in cros_ec_dt_type_to_pwm_type()
81 u16 duty) in cros_ec_pwm_set_duty() argument
83 struct cros_ec_device *ec = ec_pwm->ec; in cros_ec_pwm_set_duty()
94 msg->version = 0; in cros_ec_pwm_set_duty()
[all …]
|
| D | pwm-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
7 * with the old duty cycle and the new period. This is because the counters
9 * automatically reloaded at the end of a cycle. If this automatic reload
11 * bad cycle. This could probably be fixed by reading TCR0 just before
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
14 * possible by stopping the counters at an appropriate point in the cycle,
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
[all …]
|
| D | pwm-sl28cpld.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
30 * - The duty cycle will switch immediately and not after a complete cycle.
31 * - Depending on the actual implementation, disabling the PWM might have
[all …]
|
| D | pwm-iqs620a.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * - The period is fixed to 1 ms and is generated continuously despite changes
9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
13 * ms, the output is disabled and relies upon an external pull-down resistor
46 struct iqs62x_core *iqs62x = iqs620_pwm->iqs62x; in iqs620_pwm_init()
50 return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS, in iqs620_pwm_init()
53 ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE, in iqs620_pwm_init()
54 duty_scale - 1); in iqs620_pwm_init()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | pwm-regulator.txt | 7 predefined voltage <=> duty-cycle values must be
10 Intermediary duty-cycle values which would normally
13 the user if the assumptions made in continuous-voltage
18 regulator-{min,max}-microvolt properties to calculate
19 appropriate duty-cycle values. This allows for a much
21 voltage-table mode above. This solution does make an
22 assumption that a %50 duty-cycle value will cause the
27 --------------------
28 - compatible: Should be "pwm-regulator"
30 - pwms: PWM specification (See: ../pwm/pwm.txt)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/ |
| D | pwm-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
[all …]
|
| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
|
| D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
[all …]
|
| D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
|
| D | max31790.rst | 10 Addresses scanned: -
18 -----------
23 PWM outputs. The desired fan speeds (or PWM duty cycles) are written
24 through the I2C interface. The outputs drive "4-wire" fans directly,
28 Tachometer inputs monitor fan tachometer logic outputs for precise (+/-1%)
35 -------------
38 fan[1-12]_input RO fan tachometer speed in RPM
39 fan[1-12]_fault RO fan experienced fault
40 fan[1-6]_target RW desired fan speed in RPM
41 pwm[1-6]_enable RW regulator mode, 0=disabled (duty cycle=0%), 1=manual mode, 2=rpm mode
[all …]
|
| /kernel/linux/linux-6.6/Documentation/hwmon/ |
| D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
|
| D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
[all …]
|
| D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
23 const: pwm-vibrator
25 pwm-names:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.txt | 4 strength increases based on the duty cycle of the enable PWM channel
5 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
8 driven at fixed duty cycle. If available this is can be used to increase
12 - compatible: should contain "pwm-vibrator"
13 - pwm-names: Should contain "enable" and optionally "direction"
14 - pwms: Should contain a PWM handle for each entry in pwm-names
17 - vcc-supply: Phandle for the regulator supplying power
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
26 pinctrl-single,pins = <
32 pinctrl-single,pins = <
[all …]
|
| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-cros-ec.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * struct cros_ec_pwm_device - Driver data for EC PWM
29 * struct cros_ec_pwm - per-PWM driver data
30 * @duty_cycle: cached duty cycle
47 return -ENOMEM; in cros_ec_pwm_request()
61 static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) in cros_ec_pwm_set_duty() argument
72 msg->version = 0; in cros_ec_pwm_set_duty()
73 msg->command = EC_CMD_PWM_SET_DUTY; in cros_ec_pwm_set_duty()
74 msg->insize = 0; in cros_ec_pwm_set_duty()
75 msg->outsize = sizeof(*params); in cros_ec_pwm_set_duty()
[all …]
|
| D | pwm-iqs620a.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * - The period is fixed to 1 ms and is generated continuously despite changes
9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - The device cannot generate a 0% duty cycle. For duty cycles below 1 / 256
13 * ms, the output is disabled and relies upon an external pull-down resistor
53 if (state->polarity != PWM_POLARITY_NORMAL) in iqs620_pwm_apply()
54 return -ENOTSUPP; in iqs620_pwm_apply()
56 if (state->period < IQS620_PWM_PERIOD_NS) in iqs620_pwm_apply()
57 return -EINVAL; in iqs620_pwm_apply()
[all …]
|
| D | pwm-sl28cpld.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
30 * - The duty cycle will switch immediately and not after a complete cycle.
31 * - Depending on the actual implementation, disabling the PWM might have
[all …]
|
| /kernel/linux/linux-5.10/Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
58 ---------------
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
58 ---------------
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | pwm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum pwm_polarity - polarity of a PWM signal
13 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
14 * cycle, followed by a low signal for the remainder of the pulse
16 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
17 * cycle, followed by a high signal for the remainder of the pulse
26 * struct pwm_args - board-dependent PWM arguments
30 * This structure describes board-dependent arguments attached to a PWM
49 * struct pwm_state - state of a PWM channel
51 * @duty_cycle: PWM duty cycle (in nanoseconds)
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | pwm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * enum pwm_polarity - polarity of a PWM signal
16 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
17 * cycle, followed by a low signal for the remainder of the pulse
19 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
20 * cycle, followed by a high signal for the remainder of the pulse
29 * struct pwm_args - board-dependent PWM arguments
33 * This structure describes board-dependent arguments attached to a PWM
52 * struct pwm_state - state of a PWM channel
54 * @duty_cycle: PWM duty cycle (in nanoseconds)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/backlight/ |
| D | pwm-backlight.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight bindings
10 - Lee Jones <lee.jones@linaro.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
16 const: pwm-backlight
21 pwm-names: true
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/leds/backlight/ |
| D | pwm-backlight.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight
10 - Lee Jones <lee@kernel.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
16 const: pwm-backlight
21 pwm-names: true
[all …]
|