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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/rockchip/
Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3288-mipi-dsi
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/
Ddw_mipi_dsi_rockchip.txt1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/
Damlogic,meson-g12a-dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 - A Synopsys DesignWare MIPI DSI Host Controller IP
16 - A TOP control block controlling the Clocks & Resets of the IP
19 - $ref: dsi-controller.yaml#
24 - amlogic,meson-g12a-dw-mipi-dsi
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dsnps,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MIPI DSI host controller
10 - Philippe CORNU <philippe.cornu@st.com>
13 This document defines device tree properties for the Synopsys DesignWare MIPI
14 DSI host controller. It doesn't constitue a device tree binding specification
15 by itself but is meant to be referenced by platform-specific device tree
23 - $ref: ../dsi-controller.yaml#
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dsnps,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MIPI DSI host controller
10 - Philippe CORNU <philippe.cornu@foss.st.com>
13 This document defines device tree properties for the Synopsys DesignWare MIPI
14 DSI host controller. It doesn't constitute a device tree binding specification
15 by itself but is meant to be referenced by platform-specific device tree
23 - $ref: ../dsi-controller.yaml#
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/synopsys/
Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
226 #define VPG_DEFS(name, dsi) \ argument
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \ argument
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi; member
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
3 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
4 obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
5 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
6 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
8 obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/synopsys/
Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
226 #define VPG_DEFS(name, dsi) \ argument
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \ argument
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi; member
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
3 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
4 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
5 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
7 obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
/kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
59 bool "Rockchip specific extensions for Synopsys DW HDMI"
67 bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
71 for the Synopsys DesignWare dsi driver. If you want to
72 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
9 rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o
10 rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
11 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
12 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
13 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
14 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
15 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
16 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
[all …]
Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
264 /* dual-channel */
272 /* being a phy for other mipi hosts */
355 return -EINVAL; in max_mbps_to_parameter()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
40 bool "Rockchip specific extensions for Synopsys DW HDMI"
48 bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
53 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
8 rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
10 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
11 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
12 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
13 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
14 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
15 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
16 rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o
[all …]
Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
230 /* dual-channel */
306 return -EINVAL; in max_mbps_to_parameter()
309 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/meson/
Dmeson_dw_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #define DRIVER_NAME "meson-dw-mipi-dsi"
34 #define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
61 mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
64 0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
69 mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL); in meson_dw_mipi_dsi_hw_init()
72 writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD); in meson_dw_mipi_dsi_hw_init()
82 ret = clk_set_rate(mipi_dsi->bit_clk, in dw_mipi_dsi_phy_init()
83 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate); in dw_mipi_dsi_phy_init()
85 dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n", in dw_mipi_dsi_phy_init()
[all …]
Dmeson_encoder_dsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 return drm_bridge_attach(bridge->encoder, encoder_dsi->next_bridge, in meson_encoder_dsi_attach()
41 &encoder_dsi->bridge, flags); in meson_encoder_dsi_attach()
48 struct drm_atomic_state *state = bridge_state->base.state; in meson_encoder_dsi_atomic_enable()
49 struct meson_drm *priv = encoder_dsi->priv; in meson_encoder_dsi_atomic_enable()
54 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); in meson_encoder_dsi_atomic_enable()
62 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); in meson_encoder_dsi_atomic_enable()
68 meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode); in meson_encoder_dsi_atomic_enable()
71 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_encoder_dsi_atomic_enable()
74 priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); in meson_encoder_dsi_atomic_enable()
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/allwinner/
Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/stm/
Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
25 /* DSI digital registers & bit definitions */
29 /* DSI wrapper registers & bit definitions */
32 #define WCFGR_DSIM BIT(0) /* DSI Mode */
36 #define WCR_DSIEN BIT(3) /* DSI ENable */
60 /* dsi color format coding according to the datasheet */
80 struct dw_mipi_dsi *dsi; member
87 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
89 writel(val, dsi->base + reg); in dsi_write()
92 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) in dsi_read() argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/stm/
Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
25 /* DSI digital registers & bit definitions */
29 /* DSI wrapper registers & bit definitions */
32 #define WCFGR_DSIM BIT(0) /* DSI Mode */
36 #define WCR_DSIEN BIT(3) /* DSI ENable */
60 /* dsi color format coding according to the datasheet */
80 struct dw_mipi_dsi *dsi; member
87 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
89 writel(val, dsi->base + reg); in dsi_write()
92 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) in dsi_read() argument
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/kirin/
Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
98 struct dw_dsi dsi; member
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
191 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/kirin/
Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 Hisilicon Limited.
97 struct dw_dsi dsi; member
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
190 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]

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