| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
30 #define PRG_ETH0_EXT_RMII_MODE 4
33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
74 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
96 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
[all …]
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| D | dwmac-oxnas.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Oxford Semiconductor OXNAS DWMAC glue layer
35 #define DWMAC_LOW_TX_SOURCE 4
59 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_init() local
64 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
68 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
72 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
74 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
91 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
94 value = DWMAC_TX_VARDELAY(4) | in oxnas_dwmac_init()
[all …]
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| D | dwmac-sti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
44 * ------------------------------------------------
47 * ------------------------------------------------
49 *| | clk-125/txclk | txclk |
50 * ------------------------------------------------
52 *| | clk-125/txclk | clkgen |
54 * ------------------------------------------------
56 *| | |clkgen/phyclk-in |
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| D | dwmac-anarion.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adaptrum Anarion DWMAC glue layer
18 #define GMAC_SW_CONFIG_REG 4
29 return readl((void *)(gmac->ctl_block + reg)); in gmac_read_reg()
34 writel(val, (void *)(gmac->ctl_block + reg)); in gmac_write_reg()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
71 dev_err(&pdev->dev, "Cannot get reset region (%ld)!\n", in anarion_config_dt()
76 gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); in anarion_config_dt()
78 return ERR_PTR(-ENOMEM); in anarion_config_dt()
80 gmac->ctl_block = (uintptr_t)ctl_block; in anarion_config_dt()
[all …]
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| D | dwmac-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * DWMAC Intel header file
18 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
19 #define SERDES_PWR_ST_SHIFT 4
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
30 #define PRG_ETH0_EXT_RMII_MODE 4
33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
84 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
107 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
[all …]
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| D | dwmac-sti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
43 * ------------------------------------------------
46 * ------------------------------------------------
48 *| | clk-125/txclk | txclk |
49 * ------------------------------------------------
51 *| | clk-125/txclk | clkgen |
53 * ------------------------------------------------
55 *| | |clkgen/phyclk-in |
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| D | dwmac-visconti.c | 1 // SPDX-License-Identifier: GPL-2.0
25 #define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)
59 struct visconti_eth *dwmac = priv; in visconti_eth_fix_mac_speed() local
60 struct net_device *netdev = dev_get_drvdata(dwmac->dev); in visconti_eth_fix_mac_speed()
64 spin_lock_irqsave(&dwmac->lock, flags); in visconti_eth_fix_mac_speed()
67 val = readl(dwmac->reg + MAC_CTRL_REG); in visconti_eth_fix_mac_speed()
72 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
76 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
78 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) in visconti_eth_fix_mac_speed()
83 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
[all …]
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| D | dwmac-starfive.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive DWMAC platform driver
36 struct starfive_dwmac *dwmac = priv; in starfive_dwmac_fix_mac_speed() local
40 rate = clk_get_rate(dwmac->clk_tx); in starfive_dwmac_fix_mac_speed()
53 dev_err(dwmac->dev, "invalid speed %u\n", speed); in starfive_dwmac_fix_mac_speed()
57 err = clk_set_rate(dwmac->clk_tx, rate); in starfive_dwmac_fix_mac_speed()
59 dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); in starfive_dwmac_fix_mac_speed()
64 struct starfive_dwmac *dwmac = plat_dat->bsp_priv; in starfive_dwmac_set_mode() local
70 switch (plat_dat->mac_interface) { in starfive_dwmac_set_mode()
83 dev_err(dwmac->dev, "unsupported interface %d\n", in starfive_dwmac_set_mode()
[all …]
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| D | dwmac-anarion.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adaptrum Anarion DWMAC glue layer
18 #define GMAC_SW_CONFIG_REG 4
29 return readl(gmac->ctl_block + reg); in gmac_read_reg()
34 writel(val, gmac->ctl_block + reg); in gmac_write_reg()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
72 dev_err(&pdev->dev, "Cannot get reset region (%d)!\n", err); in anarion_config_dt()
76 gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); in anarion_config_dt()
78 return ERR_PTR(-ENOMEM); in anarion_config_dt()
80 gmac->ctl_block = ctl_block; in anarion_config_dt()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
[all …]
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| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer Device Tree Bindings
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
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| D | socfpga-dwmac.txt | 1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
12 Along with "snps,dwmac" and any applicable more detailed
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected emac splitter.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | toshiba,visconti-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba Visconti DWMAC Ethernet controller
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
17 - toshiba,visconti-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
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| D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
[all …]
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
[all …]
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| D | starfive,jh7110-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
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| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
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| D | socfpga-dwmac.txt | 1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
12 Along with "snps,dwmac" and any applicable more detailed
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected emac splitter.
[all …]
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| D | qcom,ethqos.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17 - $ref: snps,dwmac.yaml#
22 - qcom,qcs404-ethqos
23 - qcom,sa8775p-ethqos
24 - qcom,sc8280xp-ethqos
25 - qcom,sm8150-ethqos
30 reg-names:
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
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