| /kernel/linux/linux-5.10/drivers/nvmem/ |
| D | sprd-efuse.c | 39 * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
40 * and we can only access the normal efuse in kernel. So define the normal
52 * when reading or writing data to efuse memory, the controller can save double
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sprd_efuse_lock(struct sprd_efuse *efuse) in sprd_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sprd_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sprd_efuse_lock()
92 dev_err(efuse->dev, "timeout get the hwspinlock\n"); in sprd_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sprd_efuse_lock()
100 static void sprd_efuse_unlock(struct sprd_efuse *efuse) in sprd_efuse_unlock() argument
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| D | meson-mx-efuse.c | 3 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
51 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, in meson_mx_efuse_mask_bits() argument
56 data = readl(efuse->base + reg); in meson_mx_efuse_mask_bits()
60 writel(data, efuse->base + reg); in meson_mx_efuse_mask_bits()
63 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_enable() argument
67 err = clk_prepare_enable(efuse->core_clk); in meson_mx_efuse_hw_enable()
71 /* power up the efuse */ in meson_mx_efuse_hw_enable()
72 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
75 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4, in meson_mx_efuse_hw_enable()
81 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_disable() argument
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| D | sc27xx-efuse.c | 17 /* Efuse controller registers definition */
81 * efuse controller, so we need one hardware spinlock to synchronize between
84 static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse) in sc27xx_efuse_lock() argument
88 mutex_lock(&efuse->mutex); in sc27xx_efuse_lock()
90 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sc27xx_efuse_lock()
93 dev_err(efuse->dev, "timeout to get the hwspinlock\n"); in sc27xx_efuse_lock()
94 mutex_unlock(&efuse->mutex); in sc27xx_efuse_lock()
101 static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse) in sc27xx_efuse_unlock() argument
103 hwspin_unlock_raw(efuse->hwlock); in sc27xx_efuse_unlock()
104 mutex_unlock(&efuse->mutex); in sc27xx_efuse_unlock()
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| D | rockchip-efuse.c | 3 * Rockchip eFuse Driver
58 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_read() local
62 ret = clk_prepare_enable(efuse->clk); in rockchip_rk3288_efuse_read()
64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
73 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
74 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
76 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
78 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
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| D | jz4780-efuse.c | 3 * JZ4780 EFUSE Memory Support driver
10 * Currently supports JZ4780 efuse which has 8K programmable bit.
11 * Efuse is separated into seven segments as below:
72 struct jz4780_efuse *efuse = context; in jz4780_efuse_read() local
87 regmap_update_bits(efuse->map, JZ_EFUCTRL, in jz4780_efuse_read()
94 ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, in jz4780_efuse_read()
99 dev_err(efuse->dev, "Time out while reading efuse data"); in jz4780_efuse_read()
103 ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0), in jz4780_efuse_read()
119 .name = "jz4780-efuse",
142 struct jz4780_efuse *efuse; in jz4780_efuse_probe() local
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| D | Makefile | 19 nvmem_jz4780_efuse-y := jz4780-efuse.o
26 obj-$(CONFIG_MTK_EFUSE) += nvmem_mtk-efuse.o
27 nvmem_mtk-efuse-y := mtk-efuse.o
33 nvmem_rockchip_efuse-y := rockchip-efuse.o
40 obj-$(CONFIG_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o
41 nvmem-uniphier-efuse-y := uniphier-efuse.o
45 nvmem_meson_efuse-y := meson-efuse.o
47 nvmem_meson_mx_efuse-y := meson-mx-efuse.o
52 obj-$(CONFIG_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
53 nvmem-sc27xx-efuse-y := sc27xx-efuse.o
[all …]
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| /kernel/linux/linux-6.6/drivers/nvmem/ |
| D | sprd-efuse.c | 39 * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
40 * and we can only access the normal efuse in kernel. So define the normal
52 * when reading or writing data to efuse memory, the controller can save double
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sprd_efuse_lock(struct sprd_efuse *efuse) in sprd_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sprd_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sprd_efuse_lock()
92 dev_err(efuse->dev, "timeout get the hwspinlock\n"); in sprd_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sprd_efuse_lock()
100 static void sprd_efuse_unlock(struct sprd_efuse *efuse) in sprd_efuse_unlock() argument
[all …]
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| D | meson-mx-efuse.c | 3 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
50 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, in meson_mx_efuse_mask_bits() argument
55 data = readl(efuse->base + reg); in meson_mx_efuse_mask_bits()
59 writel(data, efuse->base + reg); in meson_mx_efuse_mask_bits()
62 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_enable() argument
66 err = clk_prepare_enable(efuse->core_clk); in meson_mx_efuse_hw_enable()
70 /* power up the efuse */ in meson_mx_efuse_hw_enable()
71 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
74 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4, in meson_mx_efuse_hw_enable()
80 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_disable() argument
[all …]
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| D | sc27xx-efuse.c | 16 /* Efuse controller registers definition */
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse) in sc27xx_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sc27xx_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sc27xx_efuse_lock()
92 dev_err(efuse->dev, "timeout to get the hwspinlock\n"); in sc27xx_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sc27xx_efuse_lock()
100 static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse) in sc27xx_efuse_unlock() argument
102 hwspin_unlock_raw(efuse->hwlock); in sc27xx_efuse_unlock()
103 mutex_unlock(&efuse->mutex); in sc27xx_efuse_unlock()
[all …]
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| D | rockchip-efuse.c | 3 * Rockchip eFuse Driver
58 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_read() local
62 ret = clk_prepare_enable(efuse->clk); in rockchip_rk3288_efuse_read()
64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
73 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
74 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
76 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
78 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
[all …]
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| D | jz4780-efuse.c | 3 * JZ4780 EFUSE Memory Support driver
10 * Currently supports JZ4780 efuse which has 8K programmable bit.
11 * Efuse is separated into seven segments as below:
72 struct jz4780_efuse *efuse = context; in jz4780_efuse_read() local
87 regmap_update_bits(efuse->map, JZ_EFUCTRL, in jz4780_efuse_read()
94 ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, in jz4780_efuse_read()
99 dev_err(efuse->dev, "Time out while reading efuse data"); in jz4780_efuse_read()
103 ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0), in jz4780_efuse_read()
119 .name = "jz4780-efuse",
142 struct jz4780_efuse *efuse; in jz4780_efuse_probe() local
[all …]
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| D | Makefile | 26 nvmem_jz4780_efuse-y := jz4780-efuse.o
36 nvmem_meson_efuse-y := meson-efuse.o
38 nvmem_meson_mx_efuse-y := meson-mx-efuse.o
41 obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o
42 nvmem_mtk-efuse-y := mtk-efuse.o
56 nvmem_rockchip_efuse-y := rockchip-efuse.o
59 obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
60 nvmem-sc27xx-efuse-y := sc27xx-efuse.o
66 nvmem_sprd_efuse-y := sprd-efuse.o
76 obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/aspeed/ |
| D | aspeed-bmc-delta-ahe50dc.dts | 8 efuse##n { \
10 vout-supply = <&efuse##n>; \
15 #define EFUSE(hexaddr, num) \ macro
16 efuse@##hexaddr { \
21 efuse##num: vout0 { \
22 regulator-name = __stringify(efuse##num##-reg); \
166 EFUSE(10, 03);
167 EFUSE(11, 04);
168 EFUSE(12, 01);
169 EFUSE(13, 02);
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/ |
| D | rockchip-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
7 title: Rockchip eFuse
18 - rockchip,rk3066a-efuse
19 - rockchip,rk3188-efuse
20 - rockchip,rk3228-efuse
21 - rockchip,rk3288-efuse
22 - rockchip,rk3328-efuse
23 - rockchip,rk3368-efuse
24 - rockchip,rk3399-efuse
27 - rockchip,rockchip-efuse
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| D | mediatek,efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
7 title: MediaTek efuse
10 MediaTek's efuse is used for storing calibration data, it can be accessed
22 pattern: "^efuse@[0-9a-f]+$"
28 - mediatek,mt7622-efuse
29 - mediatek,mt7623-efuse
30 - mediatek,mt7986-efuse
31 - mediatek,mt8173-efuse
32 - mediatek,mt8183-efuse
33 - mediatek,mt8186-efuse
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| D | sc27xx-efuse.txt | 1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
14 Are child nodes of eFuse, bindings of which as described in
29 efuse@380 {
30 compatible = "sprd,sc2731-efuse";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | rockchip-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
7 title: Rockchip eFuse device tree bindings
18 - rockchip,rk3066a-efuse
19 - rockchip,rk3188-efuse
20 - rockchip,rk3228-efuse
21 - rockchip,rk3288-efuse
22 - rockchip,rk3328-efuse
23 - rockchip,rk3368-efuse
24 - rockchip,rk3399-efuse
27 - rockchip,rockchip-efuse
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| D | mtk-efuse.txt | 1 = Mediatek MTK-EFUSE device tree bindings =
3 This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
7 "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
8 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
9 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
13 Are child nodes of MTK-EFUSE, bindings of which as described in
18 efuse: efuse@10206000 {
19 compatible = "mediatek,mt8173-efuse";
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| D | sc27xx-efuse.txt | 1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
14 Are child nodes of eFuse, bindings of which as described in
29 efuse@380 {
30 compatible = "sprd,sc2731-efuse";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fuse/ |
| D | nvidia,tegra20-fuse.yaml | 17 - nvidia,tegra20-efuse
18 - nvidia,tegra30-efuse
19 - nvidia,tegra114-efuse
20 - nvidia,tegra124-efuse
21 - nvidia,tegra210-efuse
22 - nvidia,tegra186-efuse
23 - nvidia,tegra194-efuse
24 - nvidia,tegra234-efuse
27 - const: nvidia,tegra132-efuse
28 - const: nvidia,tegra124-efuse
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 35 efuse: (see Optional properties)
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
47 - "efuse-address" - Contains efuse base address used to pick up ABB info.
49 "efuse-address" is required for this.
55 efuse: Mandatory if 'efuse-address' register is defined. Provides offset
56 from efuse-address to pick up ABB characteristics. Set to 0 if
57 'efuse-address' is not defined.
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 35 efuse: (see Optional properties)
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
47 - "efuse-address" - Contains efuse base address used to pick up ABB info.
49 "efuse-address" is required for this.
55 efuse: Mandatory if 'efuse-address' register is defined. Provides offset
56 from efuse-address to pick up ABB characteristics. Set to 0 if
57 'efuse-address' is not defined.
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fuse/ |
| D | nvidia,tegra20-fuse.txt | 4 - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5 must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6 "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7 For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8 For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9 "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10 For Tegra234 must contain "nvidia,tegra234-efuse".
12 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
15 nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
16 The differences between these SoCs are the size of the efuse array,
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| /kernel/linux/linux-6.6/drivers/phy/mediatek/ |
| D | phy-mtk-pcie.c | 36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
52 * @sw_efuse_supported: support software to load eFuse data
65 * @sw_efuse_en: software eFuse enable status
67 * @efuse: pointer to eFuse data for each lane
77 struct mtk_pcie_lane_efuse *efuse; member
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
106 * Initialize the phy by setting the efuse data.
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane() local
142 ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos); in mtk_pcie_efuse_read_for_lane()
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| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | ti-cpufreq.c | 57 unsigned long efuse);
77 unsigned long efuse) in amx3_efuse_xlate() argument
79 if (!efuse) in amx3_efuse_xlate()
80 efuse = opp_data->soc_data->efuse_fallback; in amx3_efuse_xlate()
82 return ~efuse; in amx3_efuse_xlate()
86 unsigned long efuse) in dra7_efuse_xlate() argument
91 * The efuse on dra7 and am57 parts contains a specific in dra7_efuse_xlate()
95 switch (efuse) { in dra7_efuse_xlate()
112 unsigned long efuse) in omap3_efuse_xlate() argument
115 return BIT(efuse); in omap3_efuse_xlate()
[all …]
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