| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-ppc4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
38 #include <asm/dcr-regs.h>
40 /* bits in mode register - bit 0 is MSb */
53 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
54 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
68 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
100 * SCPClkOut = OPBCLK/(4(CDM + 1))
102 * CDM = (OPBCLK/4*SCPClkOut) - 1
105 u8 cdm; member
142 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-ppc4xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
69 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
101 * SCPClkOut = OPBCLK/(4(CDM + 1))
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
106 u8 cdm; member
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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| /kernel/linux/linux-6.6/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_common.c | 27 { .compatible = "fsl,mpc5200-xlb", },
28 { .compatible = "mpc5200-xlb", },
32 { .compatible = "fsl,mpc5200-immr", },
33 { .compatible = "fsl,mpc5200b-immr", },
34 { .compatible = "simple-bus", },
73 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
74 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
79 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
83 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
112 { .compatible = "fsl,mpc5200-gpt", },
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_common.c | 27 { .compatible = "fsl,mpc5200-xlb", },
28 { .compatible = "mpc5200-xlb", },
32 { .compatible = "fsl,mpc5200-immr", },
33 { .compatible = "fsl,mpc5200b-immr", },
34 { .compatible = "simple-bus", },
73 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
74 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
79 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
83 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
112 { .compatible = "fsl,mpc5200-gpt", },
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
324 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
329 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
344 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
346 * transitioning to Gen-2 speed in apply_bad_link_workaround()
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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| D | pcie-designware.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include "pcie-designware.h"
66 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in dw_pcie_find_next_ext_capability()
79 while (ttl-- > 0) { in dw_pcie_find_next_ext_capability()
144 if (pci->ops->read_dbi) in dw_pcie_read_dbi()
145 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
147 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
149 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
159 if (pci->ops->write_dbi) { in dw_pcie_write_dbi()
160 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
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| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
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| D | pcie-designware.c | 1 // SPDX-License-Identifier: GPL-2.0
24 #include "pcie-designware.h"
46 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
60 pci->app_clks[i].id = dw_pcie_app_clks[i]; in dw_pcie_get_clocks()
63 pci->core_clks[i].id = dw_pcie_core_clks[i]; in dw_pcie_get_clocks()
65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, in dw_pcie_get_clocks()
66 pci->app_clks); in dw_pcie_get_clocks()
70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, in dw_pcie_get_clocks()
71 pci->core_clks); in dw_pcie_get_clocks()
79 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; in dw_pcie_get_resets()
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| /kernel/linux/linux-5.10/Documentation/gpu/ |
| D | todo.rst | 11 ----------
26 Subsystem-wide refactorings
30 ---------------------------------------------
42 --------------------------------------------------
50 non-converted driver (again virtual HW drivers for KVM are still all
62 ---------------------------------------------------------
68 avoid confusion - the other helpers in that file are all deprecated legacy
76 ----------------------------------
81 - drm_plane_helper_funcs->atomic_check gets called for enabled or disabled
85 into the drm_plane_funcs->atomic_duplicate_state functions.
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| /kernel/linux/linux-6.6/drivers/net/ethernet/mediatek/ |
| D | mtk_eth_soc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
284 __raw_writel(val, eth->base + reg); in mtk_w32()
289 return __raw_readl(eth->base + reg); in mtk_r32()
315 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/mediatek/ |
| D | mtk_eth_soc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
25 static int mtk_msg_level = -1;
27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
60 __raw_writel(val, eth->base + reg); in mtk_w32()
65 return __raw_readl(eth->base + reg); in mtk_r32()
91 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
92 return -1; in mtk_mdio_busy_wait()
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| /kernel/linux/linux-5.10/sound/sparc/ |
| D | dbri.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
25 * - https://www.freesoft.org/Linux/DBRI/
26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
31 * memory and a serial device (long pipes, no. 0-15) or between two serial
32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
34 * A timeslot defines the bit-offset and no. of bits read from a serial device.
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| /kernel/linux/linux-6.6/sound/sparc/ |
| D | dbri.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
25 * - https://www.freesoft.org/Linux/DBRI/
26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
31 * memory and a serial device (long pipes, no. 0-15) or between two serial
32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
34 * A timeslot defines the bit-offset and no. of bits read from a serial device.
[all …]
|